Re: [PATCH v1 03/35] perf vendor events: Update arrowlake events/metrics

["Falcon, Thomas" <thomas.falcon@intel.com>]

On Fri, 2025-03-21 at 23:33 -0700, Ian Rogers wrote:
> Update events from v1.07 to v1.08.
> Update event topics, metrics to be generated from the TMA spreadsheet
> and other small clean ups.
> 
> Signed-off-by: Ian Rogers <irogers@google.com>
> ---
>  .../arch/x86/arrowlake/arl-metrics.json       | 566 +++++++++---------
>  .../pmu-events/arch/x86/arrowlake/cache.json  | 148 +++++
>  .../pmu-events/arch/x86/arrowlake/memory.json |  11 +
>  .../pmu-events/arch/x86/arrowlake/other.json  | 193 ------
>  .../arch/x86/arrowlake/pipeline.json          | 163 ++++-
>  tools/perf/pmu-events/arch/x86/mapfile.csv    |   2 +-
>  6 files changed, 608 insertions(+), 475 deletions(-)
> 
> 
...

> @@ -1086,18 +1086,18 @@
>          "MetricExpr": "cpu_core@MEMORY_STALLS.MEM@ / tma_info_thread_clks",
>          "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
>          "MetricName": "tma_dram_bound",
> -        "MetricThreshold": "tma_dram_bound > 0.1 & tma_memory_bound > 0.2 & tma_backend_bound > 0.2",
> +        "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)",
>          "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS",
>          "ScaleUnit": "100%",
>          "Unit": "cpu_core"
>      },
>      {
>          "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
> -        "MetricExpr": "(cpu_core@IDQ.DSB_UOPS\\,cmask\\=0x8\\,inv\\=0x1@ + cpu_core@IDQ.DSB_UOPS@ / (cpu_core@IDQ.DSB_UOPS@ + cpu_core@IDQ.MITE_UOPS@) * (cpu_core@IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE@ - cpu_core@IDQ_BUBBLES.FETCH_LATENCY@)) / tma_info_thread_clks",
> +        "MetricExpr": "(cpu@IDQ.DSB_UOPS\\,cmask\\=0x8\\,inv\\=0x1@ + cpu_core@IDQ.DSB_UOPS@ / (cpu_core@IDQ.DSB_UOPS@ + cpu_core@IDQ.MITE_UOPS@) * (cpu_core@IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE@ - cpu_core@IDQ_BUBBLES.FETCH_LATENCY@)) / tma_info_thread_clks",
>          "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
>          "MetricName": "tma_dsb",
>          "MetricThreshold": "tma_dsb > 0.15 & tma_fetch_bandwidth > 0.2",
> -        "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline.  For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here",
> +        "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline.  For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
>          "ScaleUnit": "100%",
>          "Unit": "cpu_core"
>      },
> 

I'm seeing some errors for metrics tma_dsb, tma_lsd, and tma_mite on arrowlake. I think cpu should
be cpu_core here

$ sudo ./perf stat -M tma_dsb
event syntax error: '...THREAD!3/,cpu/IDQ.DSB_UOPS,cmask=0x8,inv=0x1,metric-
id=cpu!3IDQ.DSB_UOPS!0cmask!20x8!0inv!20x1!3/,cpu_core/topdown-fe-bound,metric-id=cpu_core!3t..'
                                  \___ Bad event or PMU

Unable to find PMU or event on a PMU of 'cpu'


>          "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit",
> -        "MetricExpr": "cpu_core@LSD.UOPS\\,cmask\\=0x8\\,inv\\=0x1@ / tma_info_thread_clks",
> +        "MetricExpr": "cpu@LSD.UOPS\\,cmask\\=0x8\\,inv\\=0x1@ / tma_info_thread_clks",
>          "MetricGroup": "FetchBW;LSD;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
>          "MetricName": "tma_lsd",
>          "MetricThreshold": "tma_lsd > 0.15 & tma_fetch_bandwidth > 0.2",
> -        "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit.  LSD typically does well sustaining Uop supply. However; in some rare cases; optimal uop-delivery could not be reached for small loops whose size (in terms of number of uops) does not suit well the LSD structure",
> +        "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit.  LSD typically does well sustaining Uop supply. However; in some rare cases; optimal uop-delivery could not be reached for small loops whose size (in terms of number of uops) does not suit well the LSD structure.",
>          "ScaleUnit": "100%",
>          "Unit": "cpu_core"
>      },
> 

...here

$ sudo ./perf stat -M tma_lsd
event syntax error: '...THREAD!3/,cpu/LSD.UOPS,cmask=0x8,inv=0x1,metric-
id=cpu!3LSD.UOPS!0cmask!20x8!0inv!20x1!3/,cpu_core/topdown-fe-bound,metric-id=cpu_core!3topdown!1..'
                                  \___ Bad event or PMU

Unable to find PMU or event on a PMU of 'cpu'


>      },
>      {
>          "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
> -        "MetricExpr": "(cpu_core@IDQ.MITE_UOPS\\,cmask\\=0x8\\,inv\\=0x1@ / tma_info_thread_clks + cpu_core@IDQ.MITE_UOPS@ / (cpu_core@IDQ.DSB_UOPS@ + cpu_core@IDQ.MITE_UOPS@) * (cpu_core@IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE@ - cpu_core@IDQ_BUBBLES.FETCH_LATENCY@)) / tma_info_thread_clks",
> +        "MetricExpr": "(cpu@IDQ.MITE_UOPS\\,cmask\\=0x8\\,inv\\=0x1@ / 2 + cpu_core@IDQ.MITE_UOPS@ / (cpu_core@IDQ.DSB_UOPS@ + cpu_core@IDQ.MITE_UOPS@) * (cpu_core@IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE@ - cpu_core@IDQ_BUBBLES.FETCH_LATENCY@)) / tma_info_thread_clks",
>          "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
>          "MetricName": "tma_mite",
>          "MetricThreshold": "tma_mite > 0.1 & tma_fetch_bandwidth > 0.2",

...and here?

$ sudo ./perf stat -M tma_mite
event syntax error: '..etiring!3/,cpu/IDQ.MITE_UOPS,cmask=0x8,inv=0x1,metric-
id=cpu!3IDQ.MITE_UOPS!0cmask!20x8!0inv!20x1!3/,cpu_core/topdown-bad-spec,metric-id=cpu_core!..'
                                  \___ Bad event or PMU

Unable to find PMU or event on a PMU of 'cpu'

Thanks,
Tom