From: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
To: Thomas Gleixner <tglx@linutronix.de>, Borislav Petkov <bp@alien8.de>
Cc: Jonathan Corbet <corbet@lwn.net>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@redhat.com>, Namhyung Kim <namhyung@kernel.org>,
x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
"Paul E. McKenney" <paulmck@kernel.org>,
Randy Dunlap <rdunlap@infradead.org>,
Andrew Morton <akpm@linux-foundation.org>,
"Maciej W. Rozycki" <macro@orcam.me.uk>,
Viresh Kumar <viresh.kumar@linaro.org>,
Vlastimil Babka <vbabka@suse.cz>, Tony Luck <tony.luck@intel.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Sean Christopherson <seanjc@google.com>,
Kyung Min Park <kyung.min.park@intel.com>,
Fenghua Yu <fenghua.yu@intel.com>,
Ricardo Neri <ricardo.neri-calderon@linux.intel.com>,
Tom Lendacky <thomas.lendacky@amd.com>,
Juergen Gross <jgross@suse.com>,
Krish Sadhukhan <krish.sadhukhan@oracle.com>,
Kan Liang <kan.liang@linux.intel.com>,
Joerg Roedel <jroedel@suse.de>,
Victor Ding <victording@google.com>,
Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>,
Pawan Gupta <pawan.kumar.gupta@linux.intel.com>,
Brijesh Singh <brijesh.singh@amd.com>,
Dave Hansen <dave.hansen@intel.com>,
Mike Rapoport <rppt@kernel.org>,
Anthony Steinhauser <asteinhauser@google.com>,
Anand K Mistry <amistry@google.com>,
Andi Kleen <ak@linux.intel.com>, Miguel Ojeda <ojeda@kernel.org>,
Nick Desaulniers <ndesaulniers@gooogle.com>,
Joe Perches <joe@perches.com>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-perf-users@vger.kernel.org
Subject: [PATCH 2/4] perf/x86/intel: Do not deploy workaround when TSX is deprecated
Date: Wed, 9 Jun 2021 14:12:38 -0700 [thread overview]
Message-ID: <4926973a8b0b2ed78217add01b5c459a92f0d511.1623272033.git-series.pawan.kumar.gupta@linux.intel.com> (raw)
In-Reply-To: <cover.2d906c322f72ec1420955136ebaa7a4c5073917c.1623272033.git-series.pawan.kumar.gupta@linux.intel.com>
Earlier workaround added by commit 400816f60c54 ("perf/x86/intel:
Implement support for TSX Force Abort") for perf counter interactions
[1] are not required on some client systems which received a microcode
update that deprecates TSX.
Bypass the perf workaround when such microcode is enumerated.
[1] Performance Monitoring Impact of Intel® Transactional Synchronization Extension Memory
http://cdrdv2.intel.com/v1/dl/getContent/604224
Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Tested-by: Neelima Krishnan <neelima.krishnan@intel.com>
---
arch/x86/events/intel/core.c | 22 ++++++++++++++++++----
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index e28892270c58..b5953e1e59a2 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -6016,10 +6016,24 @@ __init int intel_pmu_init(void)
intel_pmu_pebs_data_source_skl(pmem);
if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) {
- x86_pmu.flags |= PMU_FL_TFA;
- x86_pmu.get_event_constraints = tfa_get_event_constraints;
- x86_pmu.enable_all = intel_tfa_pmu_enable_all;
- x86_pmu.commit_scheduling = intel_tfa_commit_scheduling;
+ u64 msr;
+
+ rdmsrl(MSR_TSX_FORCE_ABORT, msr);
+ /* Systems that enumerate CPUID.RTM_ALWAYS_ABORT or
+ * support MSR_TSX_FORCE_ABORT[SDV_ENABLE_RTM] bit have
+ * TSX deprecated by default. TSX force abort hooks are
+ * not required on these systems.
+ *
+ * Only deploy the workaround when older microcode is
+ * detected.
+ */
+ if (!boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT) &&
+ !(msr & MSR_TFA_SDV_ENABLE_RTM)) {
+ x86_pmu.flags |= PMU_FL_TFA;
+ x86_pmu.get_event_constraints = tfa_get_event_constraints;
+ x86_pmu.enable_all = intel_tfa_pmu_enable_all;
+ x86_pmu.commit_scheduling = intel_tfa_commit_scheduling;
+ }
}
pr_cont("Skylake events, ");
--
git-series 0.9.1
next prev parent reply other threads:[~2021-06-09 21:12 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-09 20:57 [PATCH 0/4] TSX force abort Pawan Gupta
2021-06-09 20:58 ` [PATCH 1/4] x86/msr: Define new bits in TSX_FORCE_ABORT MSR Pawan Gupta
2021-06-11 8:39 ` Borislav Petkov
2021-06-11 21:31 ` Pawan Gupta
2021-06-09 21:12 ` Pawan Gupta [this message]
2021-06-11 7:50 ` [PATCH 2/4] perf/x86/intel: Do not deploy workaround when TSX is deprecated Borislav Petkov
2021-06-11 21:34 ` Pawan Gupta
2021-06-11 22:01 ` Borislav Petkov
2021-06-11 23:21 ` Pawan Gupta
2021-06-09 21:13 ` [PATCH 3/4] x86/tsx: Clear CPUID bits when TSX always force aborts Pawan Gupta
2021-06-11 10:03 ` Borislav Petkov
2021-06-11 21:36 ` Pawan Gupta
2021-06-09 21:14 ` [PATCH 4/4] x86/tsx: Add cmdline tsx=fake to not clear CPUID bits RTM and HLE Pawan Gupta
2021-06-11 10:06 ` Borislav Petkov
2021-06-11 21:37 ` Pawan Gupta
2021-07-06 19:52 ` Eduardo Habkost
2021-07-06 21:05 ` Paolo Bonzini
2021-07-06 21:33 ` Eduardo Habkost
2021-07-06 21:58 ` Paolo Bonzini
2021-07-07 15:08 ` Eduardo Habkost
2021-07-07 16:42 ` Jim Mattson
2021-07-07 17:08 ` Eduardo Habkost
2021-07-07 17:15 ` Jim Mattson
2021-07-07 18:23 ` Eduardo Habkost
2021-07-08 9:15 ` Paolo Bonzini
2021-07-06 21:16 ` Pawan Gupta
2021-07-06 21:19 ` Eduardo Habkost
2021-07-06 22:51 ` Pawan Gupta
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