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Wed, 12 Feb 2025 00:45:48 +0000 Message-ID: <49278389-9340-406f-ac82-204538b047f1@intel.com> Date: Tue, 11 Feb 2025 16:45:46 -0800 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 15/17] x86/cpu/intel: Bound the non-architectural constant_tsc model checks To: Dave Hansen , , Dave Hansen , Tony Luck CC: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , "Alexander Shishkin" , Jiri Olsa , Ian Rogers , Adrian Hunter , "Kan Liang" , Thomas Gleixner , Borislav Petkov , "H . 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Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Fenghua Yu , Jean Delvare , Guenter Roeck , Zhang Rui , Andrew Cooper , David Laight , , , , , References: <20250211194407.2577252-1-sohil.mehta@intel.com> <20250211194407.2577252-16-sohil.mehta@intel.com> Content-Language: en-US From: Sohil Mehta In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: BYAPR21CA0003.namprd21.prod.outlook.com (2603:10b6:a03:114::13) To BYAPR11MB3320.namprd11.prod.outlook.com (2603:10b6:a03:18::25) Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BYAPR11MB3320:EE_|PH7PR11MB6907:EE_ X-MS-Office365-Filtering-Correlation-Id: 4998d2cf-895d-47d2-cef0-08dd4afe974c X-LD-Processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|7416014|1800799024; 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Supported >> CPUs use the architectural Invariant TSC bit in CPUID.80000007. A >> Family-model check is not required for these CPUs. >> >> Prevent unnecessary confusion but restricting the model specific checks >> to CPUs that need it and moving it closer to the architectural check. >> >> Invariant TSC was likely introduced around the Nehalam timeframe on the >> Xeon side and Saltwell timeframe on the Atom side. Due to interspersed >> model numbers extend the non-architectural capability setting until >> Ivybridge to be safe. > > How about: > > X86_FEATURE_CONSTANT_TSC is a Linux-defined, synthesized feature flag. > It is used across several vendors. Intel CPUs will set the feature when > the architectural CPUID.80000007.EDX[1] bit is set. There are also some > Intel CPUs that have the X86_FEATURE_CONSTANT_TSC behavior but don't > enumerate it with the architectural bit. Those currently have a model > range check. > > Today, virtually all of the CPUs that have the CPUID bit *also* match > the "model >= 0x0e" check. This is confusing. Instead of an open-ended > check, pick some models (INTEL_IVYBRIDGE and P4_WILLAMETTE) as the end > of goofy CPUs that should enumerate the bit but don't. These models are > relatively arbitrary but conservative pick for this. > > This makes it obvious that later CPUs (like family 18+) no longer need > to synthesize X86_FEATURE_CONSTANT_TSC. > Looks much better. >> + /* Some older CPUs have invariant TSC but may not report it architecturally via 8000_0007 */ >> + if ((c->x86_vfm >= INTEL_P4_PRESCOTT && c->x86_vfm <= INTEL_P4_WILLAMETTE) || >> + (c->x86_vfm >= INTEL_CORE_YONAH && c->x86_vfm <= INTEL_IVYBRIDGE)) >> + set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); > > Please do vertically align this too. > > Would it make logical sense to do: > > if (c->x86_power & (1 << 8)) { > set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); > set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); > } else if ((c->x86_vfm >= INTEL_P4_PRESCOTT ... > > ? > > That would make it *totally* clear that it's an either/or situation. Right? > Yup, will change it. >