[PATCH 1/2] perf tools riscv: Allow get_cpuid return empty MARCH and MIMP

[PATCH 1/2] perf tools riscv: Allow get_cpuid return empty MARCH and MIMP

[Inochi Amaoto]

The T-HEAD C9xx series CPU only has MVENDOR defined, and left MARCH
and MIMP unimplemented.

To make perf support T-HEAD C9xx events. remove the restriction of
the MARCH and MIMP.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
---
 tools/perf/arch/riscv/util/header.c | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/tools/perf/arch/riscv/util/header.c b/tools/perf/arch/riscv/util/header.c
index 4a41856938a8..031899c627f6 100644
--- a/tools/perf/arch/riscv/util/header.c
+++ b/tools/perf/arch/riscv/util/header.c
@@ -55,18 +55,13 @@ static char *_get_cpuid(void)
 				goto free;
 		} else if (!strncmp(line, CPUINFO_MARCH, strlen(CPUINFO_MARCH))) {
 			marchid = _get_field(line);
-			if (!marchid)
-				goto free;
 		} else if (!strncmp(line, CPUINFO_MIMP, strlen(CPUINFO_MIMP))) {
 			mimpid = _get_field(line);
-			if (!mimpid)
-				goto free;
-
 			break;
 		}
 	}
 
-	if (!mvendorid || !marchid || !mimpid)
+	if (!mvendorid)
 		goto free;
 
 	if (asprintf(&cpuid, "%s-%s-%s", mvendorid, marchid, mimpid) < 0)
-- 
2.40.1

Re: [PATCH 1/2] perf tools riscv: Allow get_cpuid return empty MARCH and MIMP

[Nikita Shubin]

Hello Inochi Amaoto!

On Tue, 2023-05-16 at 10:37 +0800, Inochi Amaoto wrote:
> The T-HEAD C9xx series CPU only has MVENDOR defined, and left MARCH
> and MIMP unimplemented.

According to the docs you can still read them, but it's hardwired to
64h0.

How it's supposed to distinguish c906 and c910 for example ?

> 
> To make perf support T-HEAD C9xx events. remove the restriction of
> the MARCH and MIMP.
> 
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> ---
>  tools/perf/arch/riscv/util/header.c | 7 +------
>  1 file changed, 1 insertion(+), 6 deletions(-)
> 
> diff --git a/tools/perf/arch/riscv/util/header.c
> b/tools/perf/arch/riscv/util/header.c
> index 4a41856938a8..031899c627f6 100644
> --- a/tools/perf/arch/riscv/util/header.c
> +++ b/tools/perf/arch/riscv/util/header.c
> @@ -55,18 +55,13 @@ static char *_get_cpuid(void)
>                                 goto free;
>                 } else if (!strncmp(line, CPUINFO_MARCH,
> strlen(CPUINFO_MARCH))) {
>                         marchid = _get_field(line);
> -                       if (!marchid)
> -                               goto free;
>                 } else if (!strncmp(line, CPUINFO_MIMP,
> strlen(CPUINFO_MIMP))) {
>                         mimpid = _get_field(line);
> -                       if (!mimpid)
> -                               goto free;
> -
>                         break;
>                 }
>         }

What does /proc/cpuinfo shows on c9xx ? Why can't we use zeroes ?

>  
> -       if (!mvendorid || !marchid || !mimpid)
> +       if (!mvendorid)
>                 goto free;
>  
>         if (asprintf(&cpuid, "%s-%s-%s", mvendorid, marchid, mimpid)
> < 0)

Re: [PATCH 1/2] perf tools riscv: Allow get_cpuid return empty MARCH and MIMP

[Inochi Amaoto]

> > The T-HEAD C9xx series CPU only has MVENDOR defined, and left MARCH
> > and MIMP unimplemented.
>
> According to the docs you can still read them, but it's hardwired to
> 64h0.
>
> How it's supposed to distinguish c906 and c910 for example ?

It is unnecessary to distinguish c9xx, their event index is compatible.
The dtb and opensbi will final decide which event can be used.

> What does /proc/cpuinfo shows on c9xx ? Why can't we use zeroes ?

The content is as follows.

processor     : 0
hart          : 0
isa           : rv64imafdc
mmu           : sv39
uarch         : thead,c910
mvendorid     : 0x5b7
marchid       : 0x0
mimpid        : 0x0

The `mvendorid`, `marchid`, `mimpid` are the same across allwinner D1 (C906),
T-HEAD th1520 (C910) and the sophgo mango (C920). It seems T-HEAD use MCPUID
CSR to store CPU info. But this is not standard and not shown in cpuinfo.

Re: [PATCH 1/2] perf tools riscv: Allow get_cpuid return empty MARCH and MIMP

[Nikita Shubin]

On Tue, 2023-05-16 at 17:43 +0800, Inochi Amaoto wrote:
> > > The T-HEAD C9xx series CPU only has MVENDOR defined, and left
> > > MARCH
> > > and MIMP unimplemented.
> > 
> > According to the docs you can still read them, but it's hardwired
> > to
> > 64h0.
> > 
> > How it's supposed to distinguish c906 and c910 for example ?
> 
> It is unnecessary to distinguish c9xx, their event index is
> compatible.
> The dtb and opensbi will final decide which event can be used.
> 
> > What does /proc/cpuinfo shows on c9xx ? Why can't we use zeroes ?
> 
> The content is as follows.
> 
> processor     : 0
> hart          : 0
> isa           : rv64imafdc
> mmu           : sv39
> uarch         : thead,c910
> mvendorid     : 0x5b7
> marchid       : 0x0
> mimpid        : 0x0

Then why do you need first patch then ?

marchid, mimpid will never be NULL they "0x0" and "0x0" strings
respectively.

How have you tested it ? 

There no way "0x5b7-0x0000000000000000-0x[[:xdigit:]]+" will match
"0x5b7-0x0-0x0" which cpuid in your case.

Just drop this patch.

Anyway "PAGER=cat perf list pmu" gives me an empty list on licheerv.

> 
> The `mvendorid`, `marchid`, `mimpid` are the same across allwinner D1
> (C906),
> T-HEAD th1520 (C910) and the sophgo mango (C920). It seems T-HEAD use
> MCPUID
> CSR to store CPU info. But this is not standard and not shown in
> cpuinfo.
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH 1/2] perf tools riscv: Allow get_cpuid return empty MARCH and MIMP

[Inochi Amaoto]

> Then why do you need first patch then ?
>
> marchid, mimpid will never be NULL they "0x0" and "0x0" strings
> respectively.
>
> How have you tested it ?
>
> There no way "0x5b7-0x0000000000000000-0x[[:xdigit:]]+" will match
> "0x5b7-0x0-0x0" which cpuid in your case.
>
> Just drop this patch.
>
> Anyway "PAGER=cat perf list pmu" gives me an empty list on licheerv.

Sorry for this mistake, I mistook the type of the MIMP and MARCH as
unsigned long. And I write wrong MARCH id in my test container.

Anyway, I agree to drop this patch as there is no need.

[PATCH 2/2] perf vendor events riscv: add T-HEAD C9xx JSON file

[Inochi Amaoto]

Add json file of T-HEAD C9xx events.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
---
 tools/perf/pmu-events/arch/riscv/mapfile.csv  |  1 +
 .../arch/riscv/t-head/c9xx/cache.json         | 67 ++++++++++++++++++
 .../arch/riscv/t-head/c9xx/firmware.json      | 68 +++++++++++++++++++
 .../arch/riscv/t-head/c9xx/instruction.json   | 22 ++++++
 .../arch/riscv/t-head/c9xx/microarch.json     | 42 ++++++++++++
 5 files changed, 200 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/riscv/t-head/c9xx/cache.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/t-head/c9xx/firmware.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/t-head/c9xx/instruction.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/t-head/c9xx/microarch.json

diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv
index c61b3d6ef616..9fbdfcdc17ad 100644
--- a/tools/perf/pmu-events/arch/riscv/mapfile.csv
+++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
@@ -15,3 +15,4 @@
 #
 #MVENDORID-MARCHID-MIMPID,Version,Filename,EventType
 0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core
+0x5b7-0x0000000000000000-0x[[:xdigit:]]+,v1,t-head/c9xx,core
diff --git a/tools/perf/pmu-events/arch/riscv/t-head/c9xx/cache.json b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/cache.json
new file mode 100644
index 000000000000..2c6e9a904a11
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/cache.json
@@ -0,0 +1,67 @@
+[
+  {
+    "EventName": "L1_ICACHE_ACCESS",
+    "EventCode": "0x000001",
+    "BriefDescription": "L1 instruction cache access"
+  },
+  {
+    "EventName": "L1_ICACHE_MISS",
+    "EventCode": "0x000002",
+    "BriefDescription": "L1 instruction cache miss"
+  },
+  {
+    "EventName": "INST_TLB_MISS",
+    "EventCode": "0x000003",
+    "BriefDescription": "Instruction TLB (I-UTLB) miss"
+  },
+  {
+    "EventName": "DATA_TLB_MISS",
+    "EventCode": "0x000004",
+    "BriefDescription": "Data TLB (D-UTLB) miss"
+  },
+  {
+    "EventName": "JTLB_MISS",
+    "EventCode": "0x000005",
+    "BriefDescription": "JTLB access miss"
+  },
+  {
+    "EventName": "L1_DCACHE_READ_ACCESS",
+    "EventCode": "0x00000c",
+    "BriefDescription": "L1 data cache read access"
+  },
+  {
+    "EventName": "L1_DCACHE_READ_MISS",
+    "EventCode": "0x00000d",
+    "BriefDescription": "L1 data cache read miss"
+  },
+  {
+    "EventName": "L1_DCACHE_WRITE_ACCESS",
+    "EventCode": "0x00000e",
+    "BriefDescription": "L1 data cache write access"
+  },
+  {
+    "EventName": "L1_DCACHE_WRITE_MISS",
+    "EventCode": "0x00000f",
+    "BriefDescription": "L1 data cache write miss"
+  },
+  {
+    "EventName": "L2_CACHE_READ_ACCESS",
+    "EventCode": "0x000010",
+    "BriefDescription": "L2 cache read access"
+  },
+  {
+    "EventName": "L2_CACHE_READ_MISS",
+    "EventCode": "0x000011",
+    "BriefDescription": "L2 cache read miss"
+  },
+  {
+    "EventName": "L2_CACHE_WRITE_ACCESS",
+    "EventCode": "0x000012",
+    "BriefDescription": "L2 cache write access"
+  },
+  {
+    "EventName": "L2_CACHE_WRITE_MISS",
+    "EventCode": "0x000013",
+    "BriefDescription": "L2 cache write miss"
+  }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/t-head/c9xx/firmware.json b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/firmware.json
new file mode 100644
index 000000000000..9b4a032186a7
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/firmware.json
@@ -0,0 +1,68 @@
+[
+  {
+    "ArchStdEvent": "FW_MISALIGNED_LOAD"
+  },
+  {
+    "ArchStdEvent": "FW_MISALIGNED_STORE"
+  },
+  {
+    "ArchStdEvent": "FW_ACCESS_LOAD"
+  },
+  {
+    "ArchStdEvent": "FW_ACCESS_STORE"
+  },
+  {
+    "ArchStdEvent": "FW_ILLEGAL_INSN"
+  },
+  {
+    "ArchStdEvent": "FW_SET_TIMER"
+  },
+  {
+    "ArchStdEvent": "FW_IPI_SENT"
+  },
+  {
+    "ArchStdEvent": "FW_IPI_RECEIVED"
+  },
+  {
+    "ArchStdEvent": "FW_FENCE_I_SENT"
+  },
+  {
+    "ArchStdEvent": "FW_FENCE_I_RECEIVED"
+  },
+  {
+    "ArchStdEvent": "FW_SFENCE_VMA_SENT"
+  },
+  {
+    "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
+  },
+  {
+    "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
+  },
+  {
+    "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED"
+  },
+  {
+    "ArchStdEvent": "FW_HFENCE_GVMA_SENT"
+  },
+  {
+    "ArchStdEvent": "FW_HFENCE_GVMA_RECEIVED"
+  },
+  {
+    "ArchStdEvent": "FW_HFENCE_GVMA_VMID_SENT"
+  },
+  {
+    "ArchStdEvent": "FW_HFENCE_GVMA_VMID_RECEIVED"
+  },
+  {
+    "ArchStdEvent": "FW_HFENCE_VVMA_SENT"
+  },
+  {
+    "ArchStdEvent": "FW_HFENCE_VVMA_RECEIVED"
+  },
+  {
+    "ArchStdEvent": "FW_HFENCE_VVMA_ASID_SENT"
+  },
+  {
+    "ArchStdEvent": "FW_HFENCE_VVMA_ASID_RECEIVED"
+  }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/t-head/c9xx/instruction.json b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/instruction.json
new file mode 100644
index 000000000000..53c5a9838400
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/instruction.json
@@ -0,0 +1,22 @@
+[
+  {
+    "EventName": "BR_COND_MIS_PRED",
+    "EventCode": "0x000006",
+    "BriefDescription": "Conditional branch mispredict"
+  },
+  {
+    "EventName": "BR_INDIRECT_MIS_PRED",
+    "EventCode": "0x000008",
+    "BriefDescription": "Indirect branch mispredict"
+  },
+  {
+    "EventName": "BR_INDIRECT_INST",
+    "EventCode": "0x000009",
+    "BriefDescription": "Indirect branch instruction"
+  },
+  {
+    "EventName": "INST_STORE",
+    "EventCode": "0x00000b",
+    "BriefDescription": "Store instruction retired"
+  }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/t-head/c9xx/microarch.json b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/microarch.json
new file mode 100644
index 000000000000..47f94890d20f
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/microarch.json
@@ -0,0 +1,42 @@
+[
+  {
+    "EventName": "LSU_SPEC_FAIL",
+    "EventCode": "0x00000a",
+    "BriefDescription": "LSU Spec Fail"
+  },
+  {
+    "EventName": "RF_LAUNCH_FAIL",
+    "EventCode": "0x000014",
+    "BriefDescription": "Register file launch fail"
+  },
+  {
+    "EventName": "RF_REG_LAUNCH",
+    "EventCode": "0x000015",
+    "BriefDescription": "Register file reg launch"
+  },
+  {
+    "EventName": "RF_INSTRUCTION",
+    "EventCode": "0x000016",
+    "BriefDescription": "Register file instruction"
+  },
+  {
+    "EventName": "LSU_STALL_CROSS_4K",
+    "EventCode": "0x000017",
+    "BriefDescription": "LSU stall with cross 4K access"
+  },
+  {
+    "EventName": "LSU_STALL_OTHER",
+    "EventCode": "0x000018",
+    "BriefDescription": "LSU stall with other events"
+  },
+  {
+    "EventName": "LSU_SQ_DISCARD",
+    "EventCode": "0x000019",
+    "BriefDescription": "LSU SQ discard"
+  },
+  {
+    "EventName": "LSU_SQ_DISCARD_DATA",
+    "EventCode": "0x00001a",
+    "BriefDescription": "LSU SQ data discard"
+  }
+]
-- 
2.40.1

Re: [PATCH 2/2] perf vendor events riscv: add T-HEAD C9xx JSON file

[Nikita Shubin]

Hello Inochi Amaoto!

Do c906 and c910 have same HPM events ?

https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v

and


https://github.com/T-head-Semi/openc910/blob/main/C910_RTL_FACTORY/gen_rtl/pmu/rtl/ct_hpcp_top.v

Look different to me - am i missing something ?

On Tue, 2023-05-16 at 10:37 +0800, Inochi Amaoto wrote:
> Add json file of T-HEAD C9xx events.
> 
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> ---
>  tools/perf/pmu-events/arch/riscv/mapfile.csv  |  1 +
>  .../arch/riscv/t-head/c9xx/cache.json         | 67
> ++++++++++++++++++
>  .../arch/riscv/t-head/c9xx/firmware.json      | 68
> +++++++++++++++++++
>  .../arch/riscv/t-head/c9xx/instruction.json   | 22 ++++++
>  .../arch/riscv/t-head/c9xx/microarch.json     | 42 ++++++++++++
>  5 files changed, 200 insertions(+)
>  create mode 100644 tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/cache.json
>  create mode 100644 tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/firmware.json
>  create mode 100644 tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/instruction.json
>  create mode 100644 tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/microarch.json
> 
> diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv
> b/tools/perf/pmu-events/arch/riscv/mapfile.csv
> index c61b3d6ef616..9fbdfcdc17ad 100644
> --- a/tools/perf/pmu-events/arch/riscv/mapfile.csv
> +++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
> @@ -15,3 +15,4 @@
>  #
>  #MVENDORID-MARCHID-MIMPID,Version,Filename,EventType
>  0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core
> +0x5b7-0x0000000000000000-0x[[:xdigit:]]+,v1,t-head/c9xx,core
> diff --git a/tools/perf/pmu-events/arch/riscv/t-head/c9xx/cache.json
> b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/cache.json
> new file mode 100644
> index 000000000000..2c6e9a904a11
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/cache.json
> @@ -0,0 +1,67 @@
> +[
> +  {
> +    "EventName": "L1_ICACHE_ACCESS",
> +    "EventCode": "0x000001",
> +    "BriefDescription": "L1 instruction cache access"
> +  },
> +  {
> +    "EventName": "L1_ICACHE_MISS",
> +    "EventCode": "0x000002",
> +    "BriefDescription": "L1 instruction cache miss"
> +  },
> +  {
> +    "EventName": "INST_TLB_MISS",
> +    "EventCode": "0x000003",
> +    "BriefDescription": "Instruction TLB (I-UTLB) miss"
> +  },
> +  {
> +    "EventName": "DATA_TLB_MISS",
> +    "EventCode": "0x000004",
> +    "BriefDescription": "Data TLB (D-UTLB) miss"
> +  },
> +  {
> +    "EventName": "JTLB_MISS",
> +    "EventCode": "0x000005",
> +    "BriefDescription": "JTLB access miss"
> +  },
> +  {
> +    "EventName": "L1_DCACHE_READ_ACCESS",
> +    "EventCode": "0x00000c",
> +    "BriefDescription": "L1 data cache read access"
> +  },
> +  {
> +    "EventName": "L1_DCACHE_READ_MISS",
> +    "EventCode": "0x00000d",
> +    "BriefDescription": "L1 data cache read miss"
> +  },
> +  {
> +    "EventName": "L1_DCACHE_WRITE_ACCESS",
> +    "EventCode": "0x00000e",
> +    "BriefDescription": "L1 data cache write access"
> +  },
> +  {
> +    "EventName": "L1_DCACHE_WRITE_MISS",
> +    "EventCode": "0x00000f",
> +    "BriefDescription": "L1 data cache write miss"
> +  },
> +  {
> +    "EventName": "L2_CACHE_READ_ACCESS",
> +    "EventCode": "0x000010",
> +    "BriefDescription": "L2 cache read access"
> +  },
> +  {
> +    "EventName": "L2_CACHE_READ_MISS",
> +    "EventCode": "0x000011",
> +    "BriefDescription": "L2 cache read miss"
> +  },
> +  {
> +    "EventName": "L2_CACHE_WRITE_ACCESS",
> +    "EventCode": "0x000012",
> +    "BriefDescription": "L2 cache write access"
> +  },
> +  {
> +    "EventName": "L2_CACHE_WRITE_MISS",
> +    "EventCode": "0x000013",
> +    "BriefDescription": "L2 cache write miss"
> +  }
> +]
> diff --git a/tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/firmware.json b/tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/firmware.json
> new file mode 100644
> index 000000000000..9b4a032186a7
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/firmware.json
> @@ -0,0 +1,68 @@
> +[
> +  {
> +    "ArchStdEvent": "FW_MISALIGNED_LOAD"
> +  },
> +  {
> +    "ArchStdEvent": "FW_MISALIGNED_STORE"
> +  },
> +  {
> +    "ArchStdEvent": "FW_ACCESS_LOAD"
> +  },
> +  {
> +    "ArchStdEvent": "FW_ACCESS_STORE"
> +  },
> +  {
> +    "ArchStdEvent": "FW_ILLEGAL_INSN"
> +  },
> +  {
> +    "ArchStdEvent": "FW_SET_TIMER"
> +  },
> +  {
> +    "ArchStdEvent": "FW_IPI_SENT"
> +  },
> +  {
> +    "ArchStdEvent": "FW_IPI_RECEIVED"
> +  },
> +  {
> +    "ArchStdEvent": "FW_FENCE_I_SENT"
> +  },
> +  {
> +    "ArchStdEvent": "FW_FENCE_I_RECEIVED"
> +  },
> +  {
> +    "ArchStdEvent": "FW_SFENCE_VMA_SENT"
> +  },
> +  {
> +    "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
> +  },
> +  {
> +    "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
> +  },
> +  {
> +    "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED"
> +  },
> +  {
> +    "ArchStdEvent": "FW_HFENCE_GVMA_SENT"
> +  },
> +  {
> +    "ArchStdEvent": "FW_HFENCE_GVMA_RECEIVED"
> +  },
> +  {
> +    "ArchStdEvent": "FW_HFENCE_GVMA_VMID_SENT"
> +  },
> +  {
> +    "ArchStdEvent": "FW_HFENCE_GVMA_VMID_RECEIVED"
> +  },
> +  {
> +    "ArchStdEvent": "FW_HFENCE_VVMA_SENT"
> +  },
> +  {
> +    "ArchStdEvent": "FW_HFENCE_VVMA_RECEIVED"
> +  },
> +  {
> +    "ArchStdEvent": "FW_HFENCE_VVMA_ASID_SENT"
> +  },
> +  {
> +    "ArchStdEvent": "FW_HFENCE_VVMA_ASID_RECEIVED"
> +  }
> +]
> diff --git a/tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/instruction.json b/tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/instruction.json
> new file mode 100644
> index 000000000000..53c5a9838400
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/instruction.json
> @@ -0,0 +1,22 @@
> +[
> +  {
> +    "EventName": "BR_COND_MIS_PRED",
> +    "EventCode": "0x000006",
> +    "BriefDescription": "Conditional branch mispredict"
> +  },
> +  {
> +    "EventName": "BR_INDIRECT_MIS_PRED",
> +    "EventCode": "0x000008",
> +    "BriefDescription": "Indirect branch mispredict"
> +  },
> +  {
> +    "EventName": "BR_INDIRECT_INST",
> +    "EventCode": "0x000009",
> +    "BriefDescription": "Indirect branch instruction"
> +  },
> +  {
> +    "EventName": "INST_STORE",
> +    "EventCode": "0x00000b",
> +    "BriefDescription": "Store instruction retired"
> +  }
> +]
> diff --git a/tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/microarch.json b/tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/microarch.json
> new file mode 100644
> index 000000000000..47f94890d20f
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/microarch.json
> @@ -0,0 +1,42 @@
> +[
> +  {
> +    "EventName": "LSU_SPEC_FAIL",
> +    "EventCode": "0x00000a",
> +    "BriefDescription": "LSU Spec Fail"
> +  },
> +  {
> +    "EventName": "RF_LAUNCH_FAIL",
> +    "EventCode": "0x000014",
> +    "BriefDescription": "Register file launch fail"
> +  },
> +  {
> +    "EventName": "RF_REG_LAUNCH",
> +    "EventCode": "0x000015",
> +    "BriefDescription": "Register file reg launch"
> +  },
> +  {
> +    "EventName": "RF_INSTRUCTION",
> +    "EventCode": "0x000016",
> +    "BriefDescription": "Register file instruction"
> +  },
> +  {
> +    "EventName": "LSU_STALL_CROSS_4K",
> +    "EventCode": "0x000017",
> +    "BriefDescription": "LSU stall with cross 4K access"
> +  },
> +  {
> +    "EventName": "LSU_STALL_OTHER",
> +    "EventCode": "0x000018",
> +    "BriefDescription": "LSU stall with other events"
> +  },
> +  {
> +    "EventName": "LSU_SQ_DISCARD",
> +    "EventCode": "0x000019",
> +    "BriefDescription": "LSU SQ discard"
> +  },
> +  {
> +    "EventName": "LSU_SQ_DISCARD_DATA",
> +    "EventCode": "0x00001a",
> +    "BriefDescription": "LSU SQ data discard"
> +  }
> +]

Re: [PATCH 2/2] perf vendor events riscv: add T-HEAD C9xx JSON file

[Inochi Amaoto]

> Do c906 and c910 have same HPM events ?
>
> https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v
>
> and
>
>
> https://github.com/T-head-Semi/openc910/blob/main/C910_RTL_FACTORY/gen_rtl/pmu/rtl/ct_hpcp_top.v
>
> Look different to me - am i missing something ?

Yes, they as different, but event ids are compatible. See [1] p.99 and [2] p.73.

It seems I forgot extra event index from C906. I will fix in the v2.

[1] https://github.com/T-head-Semi/openc910/blob/main/doc/%E7%8E%84%E9%93%81C910%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C.pdf
[2] https://github.com/T-head-Semi/openc906/blob/main/doc/%E7%8E%84%E9%93%81C906%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C.pdf

Re: [PATCH 2/2] perf vendor events riscv: add T-HEAD C9xx JSON file

[Nikita Shubin]

On Tue, 2023-05-16 at 17:45 +0800, Inochi Amaoto wrote:
> > Do c906 and c910 have same HPM events ?
> > 
> > https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v
> > 
> > and
> > 
> > 
> > https://github.com/T-head-Semi/openc910/blob/main/C910_RTL_FACTORY/gen_rtl/pmu/rtl/ct_hpcp_top.v
> > 
> > Look different to me - am i missing something ?
> 
> Yes, they as different, but event ids are compatible. See [1] p.99
> and [2] p.73.
> 
> It seems I forgot extra event index from C906. I will fix in the v2.
> 
> [1]
> https://github.com/T-head-Semi/openc910/blob/main/doc/%E7%8E%84%E9%93%81C910%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C.pdf
> [2]
> https://github.com/T-head-Semi/openc906/blob/main/doc/%E7%8E%84%E9%93%81C906%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C.pdf

They are not the same - they are different in many ways. And c906 list
seems more complete to me.

I think you should drop wildcard (it shouldn't be used anyway) then and
name it c906.

"0x5b7-0x0-0x0,v1,t-head/c906,core" would match both c906 and c910.


> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH 2/2] perf vendor events riscv: add T-HEAD C9xx JSON file

[Inochi Amaoto]

>
> They are not the same - they are different in many ways. And c906 list
> seems more complete to me.
>

They are different, as this summary:

event id range   |  support cpu
 0x01 - 0x06     |  c906,c910,c920
 0x07            |  c906
 0x08 - 0x0a     |  c910,c920
 0x0b - 0x0f     |  c906,c910,c920
 0x10 - 0x1a     |  c910,c920
 0x1b - 0x1c     |  c910,c920 (software defined, >= 0x1b)
 0x1d - 0x2a     |  c906

> I think you should drop wildcard (it shouldn't be used anyway) then and
> name it c906.
>
> "0x5b7-0x0-0x0,v1,t-head/c906,core" would match both c906 and c910.
>

Drop wildcard is a good idea. But I choose to

RESEND Re: [PATCH 2/2] perf vendor events riscv: add T-HEAD C9xx JSON file

[Inochi Amaoto]

As my last email is correct, this is a resend.

>
> They are not the same - they are different in many ways. And c906 list
> seems more complete to me.
>

They are different, as this summary:

event id range   |  support cpu
 0x01 - 0x06     |  c906,c910,c920
 0x07            |  c906
 0x08 - 0x0a     |  c910,c920
 0x0b - 0x0f     |  c906,c910,c920
 0x10 - 0x1a     |  c910,c920
 0x1b - 0x1c     |  c910,c920 (software defined, >= 0x1b)
 0x1d - 0x2a     |  c906

This table shows it is not very different. The events of c910 and c906
are complementary.

> I think you should drop wildcard (it shouldn't be used anyway) then and
> name it c906.
>
> "0x5b7-0x0-0x0,v1,t-head/c906,core" would match both c906 and c910.
>

Drop wildcard is a good idea. But I choose to preserve t-head c9xx id,
as it cover all events for c9xx series.