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From: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>
To: Oliver Sang <oliver.sang@intel.com>
Cc: oe-lkp@lists.linux.dev, lkp@intel.com,
	Kan Liang <kan.liang@linux.intel.com>,
	linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
	Peter Zijlstra <peterz@infradead.org>,
	Ingo Molnar <mingo@redhat.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Namhyung Kim <namhyung@kernel.org>,
	Ian Rogers <irogers@google.com>,
	Adrian Hunter <adrian.hunter@intel.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Andi Kleen <ak@linux.intel.com>,
	Eranian Stephane <eranian@google.com>,
	Dapeng Mi <dapeng1.mi@intel.com>
Subject: Re: [Patch v7 02/12] perf/x86/intel: Fix NULL event access and potential PEBS record loss
Date: Mon, 6 Oct 2025 16:03:48 +0800	[thread overview]
Message-ID: <4bb0537b-8b8e-48fd-b777-0787b23a3b41@linux.intel.com> (raw)
In-Reply-To: <aN4lR1TG8Mdz5XoU@xsang-OptiPlex-9020>


On 10/2/2025 3:09 PM, Oliver Sang wrote:
> hi, Dapeng,
>
> On Tue, Sep 30, 2025 at 02:19:25PM +0800, Mi, Dapeng wrote:
> [...]
>
>> Oops, it looks previous fix was incomplete. :(
>>
>> Oliver, could you please verify the new attached patch (Please apply this
>> patch on top of the whole patch series)? Thanks a lot for your effort. 
> we confirmed the patch fixed the warning we reported.
>
> Tested-by: kernel test robot <oliver.sang@intel.com>
>
> =========================================================================================
> compiler/cpufreq_governor/kconfig/option_a/rootfs/tbox_group/test/testcase:
>   gcc-12/performance/x86_64-rhel-9.4/Socket Activity/debian-12-x86_64-phoronix/lkp-csl-2sp7/stress-ng-1.11.0/phoronix-test-suite
>
> commit:
>   0c9567b36ae6f8 ("perf/x86: Remove redundant is_x86_event() prototype")
>   a7138973beb1d1 ("perf/x86/intel: Fix NULL event access and potential PEBS record loss")
>   81248d31dd384c ("perf/x86/intel: Add counter group support for arch-PEBS")
>   54701e916f6782 ("Fixup: perf/x86/intel: Fix NULL event access waring from test robot")
>
> 0c9567b36ae6f83c a7138973beb1d124386472663cf 81248d31dd384c71c3b6a6af25a 54701e916f6782039c2ea8adb4b
> ---------------- --------------------------- --------------------------- ---------------------------
>        fail:runs  %reproduction    fail:runs  %reproduction    fail:runs  %reproduction    fail:runs
>            |             |             |             |             |             |             |
>            :6          100%           6:6          100%           6:6            0%            :20    dmesg.WARNING:at_arch/x86/events/intel/ds.c:#intel_pmu_drain_pebs_nhm

Oliver, thanks a lot for confirm this. :)



>
>
>> diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
>> index 65908880f424..3dedf7a0acf6 100644
>> --- a/arch/x86/events/intel/ds.c
>> +++ b/arch/x86/events/intel/ds.c
>> @@ -2781,9 +2781,11 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs
>> *iregs, struct perf_sample_d
>>  
>>          /* PEBS v3 has more accurate status bits */
>>          if (x86_pmu.intel_cap.pebs_format >= 3) {
>> -            for_each_set_bit(bit, (unsigned long *)&pebs_status, size)
>> +            for_each_set_bit(bit, (unsigned long *)&pebs_status, size) {
>>                  counts[bit]++;
>> -
>> +                if (counts[bit] && !events[bit])
>> +                    events[bit] = cpuc->events[bit];
>> +            }
>>              continue;
>>          }
>>  
>> @@ -2821,8 +2823,11 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs
>> *iregs, struct perf_sample_d
>>           * If collision happened, the record will be dropped.
>>           */
>>          if (pebs_status != (1ULL << bit)) {
>> -            for_each_set_bit(i, (unsigned long *)&pebs_status, size)
>> +            for_each_set_bit(i, (unsigned long *)&pebs_status, size) {
>>                  error[i]++;
>> +                if (error[i] && !events[i])
>> +                    events[i] = cpuc->events[i];
>> +            }
>>              continue;
>>          }
>>

  reply	other threads:[~2025-10-06  8:03 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-28  1:34 [Patch v7 00/12] arch-PEBS enabling for Intel platforms Dapeng Mi
2025-08-28  1:34 ` [Patch v7 01/12] perf/x86: Remove redundant is_x86_event() prototype Dapeng Mi
2025-08-28  1:34 ` [Patch v7 02/12] perf/x86/intel: Fix NULL event access and potential PEBS record loss Dapeng Mi
2025-09-08  8:43   ` kernel test robot
2025-09-08  9:05     ` Mi, Dapeng
2025-09-28  6:00       ` Mi, Dapeng
2025-09-30  5:19         ` Oliver Sang
2025-09-30  6:19           ` Mi, Dapeng
2025-10-02  7:09             ` Oliver Sang
2025-10-06  8:03               ` Mi, Dapeng [this message]
2025-08-28  1:34 ` [Patch v7 03/12] perf/x86/intel: Replace x86_pmu.drain_pebs calling with static call Dapeng Mi
2025-08-28  1:34 ` [Patch v7 04/12] perf/x86/intel: Correct large PEBS flag check Dapeng Mi
2025-08-28  1:34 ` [Patch v7 05/12] perf/x86/intel: Initialize architectural PEBS Dapeng Mi
2025-08-28  1:34 ` [Patch v7 06/12] perf/x86/intel/ds: Factor out PEBS record processing code to functions Dapeng Mi
2025-08-28  1:34 ` [Patch v7 07/12] perf/x86/intel/ds: Factor out PEBS group " Dapeng Mi
2025-08-28  1:34 ` [Patch v7 08/12] perf/x86/intel: Process arch-PEBS records or record fragments Dapeng Mi
2025-08-28  1:34 ` [Patch v7 09/12] perf/x86/intel: Allocate arch-PEBS buffer and initialize PEBS_BASE MSR Dapeng Mi
2025-08-28  1:34 ` [Patch v7 10/12] perf/x86/intel: Update dyn_constranit base on PEBS event precise level Dapeng Mi
2025-08-28  1:34 ` [Patch v7 11/12] perf/x86/intel: Setup PEBS data configuration and enable legacy groups Dapeng Mi
2025-08-28  1:34 ` [Patch v7 12/12] perf/x86/intel: Add counter group support for arch-PEBS Dapeng Mi
2025-09-19  5:55 ` [Patch v7 00/12] arch-PEBS enabling for Intel platforms Mi, Dapeng
2025-10-09  8:35 ` Mi, Dapeng

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