Re: [PATCH 07/12] perf arm_spe: Refine memory level filling

[James Clark <james.clark@linaro.org>]

On 13/06/2025 4:53 pm, Leo Yan wrote:
> This commit introduces macros for detecting cache level and cache miss.
> 
> Populates the 'mem_lvl_num' field which is a later added attribute for
> representing memory level. Set NA ("not available") to memory levels if
> memory hierarchy info is absent.
> 
> Signed-off-by: Leo Yan <leo.yan@arm.com>

Reviewed-by: James Clark <james.clark@linaro.org>

> ---
>   tools/perf/util/arm-spe.c | 32 +++++++++++++++++++++-----------
>   1 file changed, 21 insertions(+), 11 deletions(-)
> 
> diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c
> index 55b8391990467c8b7818bb63de3545d94d021bb7..b2296cd025382ea36820641164ec71b13a4e7a0e 100644
> --- a/tools/perf/util/arm-spe.c
> +++ b/tools/perf/util/arm-spe.c
> @@ -39,6 +39,15 @@
>   
>   #define is_ldst_op(op)		(!!((op) & ARM_SPE_OP_LDST))
>   
> +#define ARM_SPE_CACHE_EVENT(lvl) \
> +	(ARM_SPE_##lvl##_ACCESS | ARM_SPE_##lvl##_MISS)
> +
> +#define arm_spe_is_cache_level(type, lvl) \
> +	((type) & ARM_SPE_CACHE_EVENT(lvl))
> +
> +#define arm_spe_is_cache_miss(type, lvl) \
> +	((type) & ARM_SPE_##lvl##_MISS)
> +
>   struct arm_spe {
>   	struct auxtrace			auxtrace;
>   	struct auxtrace_queues		queues;
> @@ -822,20 +831,21 @@ static const struct data_source_handle data_source_handles[] = {
>   static void arm_spe__synth_memory_level(const struct arm_spe_record *record,
>   					union perf_mem_data_src *data_src)
>   {
> -	if (record->type & (ARM_SPE_LLC_ACCESS | ARM_SPE_LLC_MISS)) {
> +	if (arm_spe_is_cache_level(record->type, LLC)) {
>   		data_src->mem_lvl = PERF_MEM_LVL_L3;
> -
> -		if (record->type & ARM_SPE_LLC_MISS)
> -			data_src->mem_lvl |= PERF_MEM_LVL_MISS;
> -		else
> -			data_src->mem_lvl |= PERF_MEM_LVL_HIT;
> -	} else if (record->type & (ARM_SPE_L1D_ACCESS | ARM_SPE_L1D_MISS)) {
> +		data_src->mem_lvl |= arm_spe_is_cache_miss(record->type, LLC) ?
> +				     PERF_MEM_LVL_MISS : PERF_MEM_LVL_HIT;
> +		data_src->mem_lvl_num = PERF_MEM_LVLNUM_L3;
> +	} else if (arm_spe_is_cache_level(record->type, L1D)) {
>   		data_src->mem_lvl = PERF_MEM_LVL_L1;
> +		data_src->mem_lvl |= arm_spe_is_cache_miss(record->type, L1D) ?
> +				     PERF_MEM_LVL_MISS : PERF_MEM_LVL_HIT;
> +		data_src->mem_lvl_num = PERF_MEM_LVLNUM_L1;
> +	}
>   
> -		if (record->type & ARM_SPE_L1D_MISS)
> -			data_src->mem_lvl |= PERF_MEM_LVL_MISS;
> -		else
> -			data_src->mem_lvl |= PERF_MEM_LVL_HIT;
> +	if (!data_src->mem_lvl) {
> +		data_src->mem_lvl = PERF_MEM_LVL_NA;
> +		data_src->mem_lvl_num = PERF_MEM_LVLNUM_NA;
>   	}
>   
>   	if (record->type & ARM_SPE_REMOTE_ACCESS)
>