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From: Manuel Selva <manuel.selva@insa-lyon.fr>
To: linux-perf-users@vger.kernel.org
Subject: Link between Intel documentation events and perf list events
Date: Mon, 01 Jul 2013 18:10:44 +0200	[thread overview]
Message-ID: <51D1AA04.7060403@insa-lyon.fr> (raw)

Hi all,

I am starting to deal with performance registers on an Intel core 
i5-2520M dual core (and hyperthreaded) processor. In this context I 
reached the CPUID x86 instruction. Playing with this instruction I am 
able to get some information about my cpu performance monitoring unit. 
According to this instruction my Last-level cache misses event is available.

My question is about the link between events reported in Intel 
documentation and events listed by perf list. Is the perf list 
cache-misses event the same than the one mentioned as Last-level cache 
missesin Intel documentation ?

Thanks,

--------
Manu

             reply	other threads:[~2013-07-01 16:10 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-07-01 16:10 Manuel Selva [this message]
2013-07-02  3:55 ` Link between Intel documentation events and perf list events Andi Kleen
2013-07-02  7:53   ` Manuel Selva
2013-07-02 12:39     ` Andreas Hollmann
2013-07-02 13:33       ` Manuel Selva
2013-07-02 14:49         ` Andi Kleen
2013-07-03  9:06           ` Manuel Selva
2013-07-03 13:28             ` Andi Kleen
2013-07-03 14:02               ` Manuel Selva
     [not found]   ` <51D28568.8070904@insa-lyon.fr>
2013-07-02 14:41     ` Andi Kleen

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