Re: Sample memory references with at least a given latency?

[Manuel Selva <selva.manuel@gmail.com>]

Hi Harald,

You are right, the perf mem tool dosn't support stting the latency 
threshold. It should be a very easy first contribution to kernel for 
myself ;-)

Regarding the timestamp, I nver need such information, but as you said 
you can't tll to the hardware (on Intel I mean) to record it along with 
processor state information. I don't know how th kernel part of perf 
configure PEBS, but why would the kernel pay the overhead of an 
interrupt by using 1 slot buffers ? Only for recording timestamp ?

----
Manu

On 02/04/2015 03:20 PM, Harald Servat wrote:
>
> Hello Manuel,
>
>    I'm running Linux 3.11 but I don't see a way to setup the latency
> threshold there. My option flags include:
>
>         -t, --type=
>         -D, --dump-raw-samples=
>         -x, --field-separator
>         -C, --cpu-list
>
>    so I guess that this option is not implemented in perf (at least on
> 3.11). So I need to capture all the samples and then discard those that
> surpass that threshold.
>
>    Going back into your example, is it possible to capture / show the
> timestamp for the captured samples? I've seen the Intel documentation,
> and there aren't timestamps in PEBS entries so that may require
> additional work. IIRC, someone of the list told me that perf allocates a
> 1-entry PEBS buffer so every time PEBS fills it, perf somehow gets an
> interrupt indicating that it has to flush it. This way, perf can
> attribute a timestamp to that sample also.
>
> Thank you very much!
>
>
> On 04/02/15 15:00, Manuel Selva wrote:
>> Hi Harald,
>>
>> Yes you can with the "perf mem" tool. It has been introduced in kernel
>> 3.10 (correct me if I am wrong, not very sure about that). It's built on
>> top of perf mem record and perf mem report but hide for you the
>> complxity of choosing the memory events . See "man perf mem" for th
>> details.
>>
>> ----------
>> Manuel
>>
>>
>>
>> 2015-02-04 13:48 GMT+01:00 Harald Servat <harald.servat@bsc.es
>> <mailto:harald.servat@bsc.es>>:
>>
>>     Hello list,
>>
>>        is there any way to configure perf to sample memory references
>>     through PEBS and enable the Load Latency Performance Monitoring
>>     Facility (section 18.7.1.2 from the Intel 64 and IA-32 Architectures
>>     Software Developer's Manual).
>>
>>     Thank you very much in advance.
>>
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