From: Manuel Selva <manuel.selva@insa-lyon.fr>
To: linux-perf-users@vger.kernel.org
Subject: Intel load latency facility
Date: Tue, 07 Apr 2015 14:13:19 +0200 [thread overview]
Message-ID: <5523C9DF.6060907@insa-lyon.fr> (raw)
Hi all,
I am using PEBS along with the load latency facility as described in the
chapter 18.7.1.2 of the SDM. I always thought that this feature only
allowed to sample memory loads accesses coming from data accesses and
not code. I am today getting results that may indicate that's not true.
Before deeging into this results, and because I am almost sure that the
answer is no, I am asking it here: does Intel PEBS + load latency
facility samples memory accesses coming from the instruction fetcher ?
Regards,
-----
Manuel
reply other threads:[~2015-04-07 12:19 UTC|newest]
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