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X-CSE-ConnectionGUID: x3MVrbs0TsKgXTEC9ATLVw== X-CSE-MsgGUID: MPdLTRUTRHSqrgFtmukMtw== X-IronPort-AV: E=McAfee;i="6700,10204,11235"; a="29590861" X-IronPort-AV: E=Sophos;i="6.11,230,1725346800"; d="scan'208";a="29590861" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2024 17:52:23 -0700 X-CSE-ConnectionGUID: Fh8opea2Tumn8ezYh4QYyw== X-CSE-MsgGUID: fYA9z0wVS6aPricdlmZwzQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,230,1725346800"; d="scan'208";a="80750176" Received: from dapengmi-mobl1.ccr.corp.intel.com (HELO [10.125.240.3]) ([10.125.240.3]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2024 17:52:17 -0700 Message-ID: <55be834b-b489-49c7-b975-66f09f2244d3@linux.intel.com> Date: Fri, 25 Oct 2024 08:52:15 +0800 Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v3 15/58] perf/x86: Support switch_interrupt interface To: "Chen, Zide" , Colton Lewis , Mingwei Zhang Cc: seanjc@google.com, pbonzini@redhat.com, xiong.y.zhang@intel.com, kan.liang@intel.com, zhenyuw@linux.intel.com, manali.shukla@amd.com, sandipan.das@amd.com, jmattson@google.com, eranian@google.com, irogers@google.com, namhyung@kernel.org, gce-passthrou-pmu-dev@google.com, samantha.alt@intel.com, zhiyuan.lv@intel.com, yanfei.xu@intel.com, like.xu.linux@gmail.com, peterz@infradead.org, rananta@google.com, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org References: <17f0f408-459a-4dc2-bad4-c697f782117c@intel.com> Content-Language: en-US From: "Mi, Dapeng" In-Reply-To: <17f0f408-459a-4dc2-bad4-c697f782117c@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 10/25/2024 3:45 AM, Chen, Zide wrote: > > On 9/9/2024 3:11 PM, Colton Lewis wrote: >> Mingwei Zhang writes: >> >>> From: Kan Liang >>> Implement switch_interrupt interface for x86 PMU, switch PMI to dedicated >>> KVM_GUEST_PMI_VECTOR at perf guest enter, and switch PMI back to >>> NMI at perf guest exit. >>> Signed-off-by: Xiong Zhang >>> Signed-off-by: Kan Liang >>> Tested-by: Yongwei Ma >>> Signed-off-by: Mingwei Zhang >>> --- >>>   arch/x86/events/core.c | 11 +++++++++++ >>>   1 file changed, 11 insertions(+) >>> diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c >>> index 5bf78cd619bf..b17ef8b6c1a6 100644 >>> --- a/arch/x86/events/core.c >>> +++ b/arch/x86/events/core.c >>> @@ -2673,6 +2673,15 @@ static bool x86_pmu_filter(struct pmu *pmu, int >>> cpu) >>>       return ret; >>>   } >>> +static void x86_pmu_switch_interrupt(bool enter, u32 guest_lvtpc) >>> +{ >>> +    if (enter) >>> +        apic_write(APIC_LVTPC, APIC_DM_FIXED | KVM_GUEST_PMI_VECTOR | >>> +               (guest_lvtpc & APIC_LVT_MASKED)); >>> +    else >>> +        apic_write(APIC_LVTPC, APIC_DM_NMI); >>> +} >>> + >> Similar issue I point out in an earlier patch. #define >> KVM_GUEST_PMI_VECTOR is guarded by CONFIG_KVM but this code is not, >> which can result in compile errors. > Since KVM_GUEST_PMI_VECTOR and the interrupt handler are owned by KVM, > how about to simplify it to: > > static void x86_pmu_switch_guest_ctx(bool enter, void *data) > { > if (enter) > apic_write(APIC_LVTPC, *(u32 *)data); > ... > } > > In KVM side: > perf_guest_enter(whatever_lvtpc_value_it_decides); Good point. Would address in v4. > > >>>   static struct pmu pmu = { >>>       .pmu_enable        = x86_pmu_enable, >>>       .pmu_disable        = x86_pmu_disable, >>> @@ -2702,6 +2711,8 @@ static struct pmu pmu = { >>>       .aux_output_match    = x86_pmu_aux_output_match, >>>       .filter            = x86_pmu_filter, >>> + >>> +    .switch_interrupt    = x86_pmu_switch_interrupt, >>>   }; >>>   void arch_perf_update_userpage(struct perf_event *event,