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X-CSE-ConnectionGUID: goCbicWATteKyIkEgBirAQ== X-CSE-MsgGUID: 1Rq/7vS2RleKecJmAc3jmw== X-IronPort-AV: E=McAfee;i="6600,9927,11041"; a="12198053" X-IronPort-AV: E=Sophos;i="6.07,195,1708416000"; d="scan'208";a="12198053" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Apr 2024 23:03:12 -0700 X-CSE-ConnectionGUID: ECa57ormQ4CcC5eP0sbrnw== X-CSE-MsgGUID: KMUUNdRCQZm6KYIzr+9rbw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,195,1708416000"; d="scan'208";a="52300920" Received: from xiongzha-mobl1.ccr.corp.intel.com (HELO [10.124.244.162]) ([10.124.244.162]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Apr 2024 23:03:07 -0700 Message-ID: <57dba444-5cb9-4128-8a16-a6924f6f2e67@linux.intel.com> Date: Fri, 12 Apr 2024 14:03:04 +0800 Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH 06/41] perf: x86: Add function to switch PMI handler Content-Language: en-US To: Sean Christopherson Cc: pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, Xiong Zhang References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> <20240126085444.324918-7-xiong.y.zhang@linux.intel.com> From: "Zhang, Xiong Y" In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 4/12/2024 3:34 AM, Sean Christopherson wrote: > On Thu, Apr 11, 2024, Sean Christopherson wrote: >> On Fri, Jan 26, 2024, Xiong Zhang wrote: >>> From: Xiong Zhang >>> >>> Add function to switch PMI handler since passthrough PMU and host PMU will >>> use different interrupt vectors. >>> >>> Signed-off-by: Xiong Zhang >>> Signed-off-by: Mingwei Zhang >>> --- >>> arch/x86/events/core.c | 15 +++++++++++++++ >>> arch/x86/include/asm/perf_event.h | 3 +++ >>> 2 files changed, 18 insertions(+) >>> >>> diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c >>> index 40ad1425ffa2..3f87894d8c8e 100644 >>> --- a/arch/x86/events/core.c >>> +++ b/arch/x86/events/core.c >>> @@ -701,6 +701,21 @@ struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data) >>> } >>> EXPORT_SYMBOL_GPL(perf_guest_get_msrs); >>> >>> +void perf_guest_switch_to_host_pmi_vector(void) >>> +{ >>> + lockdep_assert_irqs_disabled(); >>> + >>> + apic_write(APIC_LVTPC, APIC_DM_NMI); >>> +} >>> +EXPORT_SYMBOL_GPL(perf_guest_switch_to_host_pmi_vector); >>> + >>> +void perf_guest_switch_to_kvm_pmi_vector(void) >>> +{ >>> + lockdep_assert_irqs_disabled(); >>> + >>> + apic_write(APIC_LVTPC, APIC_DM_FIXED | KVM_VPMU_VECTOR); >>> +} >>> +EXPORT_SYMBOL_GPL(perf_guest_switch_to_kvm_pmi_vector); >> >> Why slice and dice the context switch if it's all in perf? Just do this in >> perf_guest_enter(). > > Ah, because perf_guest_enter() isn't x86-specific. > > That can be solved by having the exported APIs be arch specific, e.g. > x86_perf_guest_enter(), and making perf_guest_enter() a perf-internal API. > > That has the advantage of making it impossible to call perf_guest_enter() on an > unsupported architecture (modulo perf bugs). > Make sense. I will try it. thanks