From: Dave Jiang <dave.jiang@intel.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
linux-cxl@vger.kernel.org,
Dan Williams <dan.j.williams@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Ben Widawsky <bwidawsk@kernel.org>,
linux-perf-users@vger.kernel.org, Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>
Cc: linuxarm@huawei.com
Subject: Re: [RFC PATCH v2 1/4] cxl: Add function to count regblocks of a given type.
Date: Thu, 22 Sep 2022 13:19:41 -0700 [thread overview]
Message-ID: <590441ff-df5c-b52a-2da3-4aa42f5ea3e9@intel.com> (raw)
In-Reply-To: <20220824103617.21781-2-Jonathan.Cameron@huawei.com>
On 8/24/2022 3:36 AM, Jonathan Cameron wrote:
> Until the recently release CXL 3.0 specification, there
> was only ever one instance of any given register block pointed
> to by the Register Block Locator DVSEC. Now, the specification allows
> for multiple CXL PMU instances, each with their own register block.
>
> To enable this add an index parameter to cxl_find_regblock()
> and use that to implement cxl_count_regblock().
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
> drivers/cxl/core/pci.c | 2 +-
> drivers/cxl/core/port.c | 2 +-
> drivers/cxl/core/regs.c | 35 ++++++++++++++++++++++++++++++++---
> drivers/cxl/cxl.h | 3 ++-
> drivers/cxl/pci.c | 2 +-
> 5 files changed, 37 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index 9240df53ed87..f29cdc9df330 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -49,7 +49,7 @@ static int match_add_dports(struct pci_dev *pdev, void *data)
> &lnkcap))
> return 0;
>
> - rc = cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
> + rc = cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map, 0);
> if (rc)
> dev_dbg(&port->dev, "failed to find component registers\n");
>
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index bffde862de0b..1629c7a4033f 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -1235,7 +1235,7 @@ static resource_size_t find_component_registers(struct device *dev)
>
> pdev = to_pci_dev(dev);
>
> - cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
> + cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map, 0);
> return cxl_regmap_to_base(pdev, &map);
> }
>
> diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
> index 39a129c57d40..2f651211d120 100644
> --- a/drivers/cxl/core/regs.c
> +++ b/drivers/cxl/core/regs.c
> @@ -262,6 +262,7 @@ static void cxl_decode_regblock(u32 reg_lo, u32 reg_hi,
> * @pdev: The CXL PCI device to enumerate.
> * @type: Register Block Indicator id
> * @map: Enumeration output, clobbered on error
> + * @index: Index into which particular instance of a regblock we want.
> *
> * Return: 0 if register block enumerated, negative error code otherwise
> *
> @@ -269,9 +270,10 @@ static void cxl_decode_regblock(u32 reg_lo, u32 reg_hi,
> * by @type.
> */
> int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
> - struct cxl_register_map *map)
> + struct cxl_register_map *map, int index)
> {
> u32 regloc_size, regblocks;
> + int instance = 0;
> int regloc, i;
>
> map->block_offset = U64_MAX;
> @@ -294,11 +296,38 @@ int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
>
> cxl_decode_regblock(reg_lo, reg_hi, map);
>
> - if (map->reg_type == type)
> - return 0;
> + if (map->reg_type == type) {
> + if (index == instance)
> + return 0;
> + instance++;
> + }
> }
>
> map->block_offset = U64_MAX;
> return -ENODEV;
> }
> EXPORT_SYMBOL_NS_GPL(cxl_find_regblock, CXL);
> +
> +/**
> + * cxl_count_regblock() - Count instances of a given regblock type.
> + * @pdev: The CXL PCI device to enumerate.
> + * @type: Register Block Indicator id
> + *
> + * Some regblocks may be repeated. Count how many instances.
> + *
> + * Return: count of matching regblocks.
> + */
> +int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type)
> +{
> + struct cxl_register_map map;
> + int rc, count = 0;
> +
> + while (1) {
> + rc = cxl_find_regblock(pdev, type, &map, count);
> + if (rc)
> + return count;
> + count++;
> + }
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_count_regblock, CXL);
> +
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index f680450f0b16..5a1bcdbda654 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -216,8 +216,9 @@ int cxl_map_device_regs(struct pci_dev *pdev,
> struct cxl_register_map *map);
>
> enum cxl_regloc_type;
> +int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type);
> int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
> - struct cxl_register_map *map);
> + struct cxl_register_map *map, int index);
> void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
> resource_size_t length);
>
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index faeb5d9d7a7a..1758380247ec 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -373,7 +373,7 @@ static int cxl_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
> {
> int rc;
>
> - rc = cxl_find_regblock(pdev, type, map);
> + rc = cxl_find_regblock(pdev, type, map, 0);
> if (rc)
> return rc;
>
next prev parent reply other threads:[~2022-09-22 20:19 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-24 10:36 [RFC PATCH v2 0/4] CXL 3.0 Performance Monitoring Unit support Jonathan Cameron
2022-08-24 10:36 ` [RFC PATCH v2 1/4] cxl: Add function to count regblocks of a given type Jonathan Cameron
2022-09-22 20:19 ` Dave Jiang [this message]
2022-08-24 10:36 ` [RFC PATCH v2 2/4] cxl/pci: Find and register CXL PMU devices Jonathan Cameron
2022-09-01 22:36 ` Dave Jiang
2022-10-18 11:19 ` Jonathan Cameron
2022-10-21 17:26 ` Dave Jiang
2022-08-24 10:36 ` [RFC PATCH v2 3/4] cxl: CXL Performance Monitoring Unit driver Jonathan Cameron
2022-09-22 20:19 ` Dave Jiang
2022-10-18 11:26 ` Jonathan Cameron
2022-08-24 10:36 ` [RFC PATCH v2 4/4] docs: perf: Minimal introduction the the CXL PMU device and driver Jonathan Cameron
2022-09-22 20:41 ` Dave Jiang
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