From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25754C433F5 for ; Tue, 14 Sep 2021 08:24:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EADAF60F24 for ; Tue, 14 Sep 2021 08:24:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229562AbhINIZl (ORCPT ); Tue, 14 Sep 2021 04:25:41 -0400 Received: from foss.arm.com ([217.140.110.172]:40964 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229458AbhINIZk (ORCPT ); Tue, 14 Sep 2021 04:25:40 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0E0A61FB; Tue, 14 Sep 2021 01:24:23 -0700 (PDT) Received: from [10.57.94.84] (unknown [10.57.94.84]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 617863F719; Tue, 14 Sep 2021 01:24:19 -0700 (PDT) Subject: Re: [PATCH v5 3/9] coresight: tmc-etf: Add comment for store ordering To: Leo Yan , Arnaldo Carvalho de Melo , Peter Zijlstra , Adrian Hunter , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Thomas Gleixner , Borislav Petkov , "H. Peter Anvin" , Mathieu Poirier , Mike Leach , Michael Petlan , "Frank Ch. Eigler" , Song Liu , x86@kernel.org, =?UTF-8?Q?Daniel_D=c3=adaz?= , Andrii Nakryiko , Alexei Starovoitov , Sedat Dilek , Andi Kleen , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, coresight@lists.linaro.org References: <20210809111407.596077-1-leo.yan@linaro.org> <20210809111407.596077-4-leo.yan@linaro.org> From: Suzuki K Poulose Message-ID: <60c20d8e-4386-5c54-4607-d9399713d2ef@arm.com> Date: Tue, 14 Sep 2021 09:24:18 +0100 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: <20210809111407.596077-4-leo.yan@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-perf-users@vger.kernel.org On 09/08/2021 12:14, Leo Yan wrote: > Since the function CS_LOCK() has contained memory barrier mb(), it > ensures the visibility of the AUX trace data before updating the > aux_head, thus it's needless to add any explicit barrier anymore. > > Add comment to make clear for the barrier usage for ETF. > > Signed-off-by: Leo Yan > --- > drivers/hwtracing/coresight/coresight-tmc-etf.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c > index cd0fb7bfba68..8debd4f40f06 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c > @@ -553,6 +553,11 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev, > if (buf->snapshot) > handle->head += to_read; > > + /* > + * CS_LOCK() contains mb() so it can ensure visibility of the AUX trace > + * data before the aux_head is updated via perf_aux_output_end(), which > + * is expected by the perf ring buffer. > + */ > CS_LOCK(drvdata->base); > out: > spin_unlock_irqrestore(&drvdata->spinlock, flags); > I will queue this. Thanks Suzuki