From: Dan Williams <dan.j.williams@intel.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Namhyung Kim <namhyung@gmail.com>,
Liang Kan <kan.liang@linux.intel.com>,
<linux-cxl@vger.kernel.org>, <peterz@infradead.org>
Cc: <mingo@reresetdhat.com>, <acme@kernel.org>,
<mark.rutland@arm.com>, <will@kernel.org>,
<dan.j.williams@intel.com>, <linuxarm@huawei.com>,
<linux-perf-users@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
Davidlohr Bueso <dave@stgolabs.net>,
Dave Jiang <dave.jiang@intel.com>
Subject: RE: [PATCH v8 3/5] cxl/pci: Find and register CXL PMU devices
Date: Sun, 25 Jun 2023 17:46:53 -0700 [thread overview]
Message-ID: <6498dffd2e228_8e17829465@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <20230531110011.13963-4-Jonathan.Cameron@huawei.com>
Jonathan Cameron wrote:
> CXL PMU devices can be found from entries in the Register
> Locator DVSEC.
>
> Reviewed-by: Dan Williams <dan.j.williams@intel.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> drivers/cxl/core/Makefile | 1 +
> drivers/cxl/core/core.h | 1 +
> drivers/cxl/core/pmu.c | 68 +++++++++++++++++++++++++++++++++++++++
> drivers/cxl/core/port.c | 2 ++
> drivers/cxl/core/regs.c | 16 +++++++++
> drivers/cxl/cxl.h | 13 ++++++++
> drivers/cxl/cxlpci.h | 1 +
> drivers/cxl/pci.c | 26 ++++++++++++++-
> drivers/cxl/pmu.h | 28 ++++++++++++++++
> 9 files changed, 155 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile
> index ca4ae31d8f57..1f66b5d4d935 100644
> --- a/drivers/cxl/core/Makefile
> +++ b/drivers/cxl/core/Makefile
> @@ -12,5 +12,6 @@ cxl_core-y += memdev.o
> cxl_core-y += mbox.o
> cxl_core-y += pci.o
> cxl_core-y += hdm.o
> +cxl_core-y += pmu.o
One small addition I will make to this patch is to fix the cxl_test
build with the following complimentary change:
diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild
index 6f9347ade82c..aa0ca7095a64 100644
--- a/tools/testing/cxl/Kbuild
+++ b/tools/testing/cxl/Kbuild
@@ -57,6 +57,7 @@ cxl_core-y += $(CXL_CORE_SRC)/memdev.o
cxl_core-y += $(CXL_CORE_SRC)/mbox.o
cxl_core-y += $(CXL_CORE_SRC)/pci.o
cxl_core-y += $(CXL_CORE_SRC)/hdm.o
+cxl_core-y += $(CXL_CORE_SRC)/pmu.o
cxl_core-$(CONFIG_TRACING) += $(CXL_CORE_SRC)/trace.o
cxl_core-$(CONFIG_CXL_REGION) += $(CXL_CORE_SRC)/region.o
cxl_core-y += config_check.o
next prev parent reply other threads:[~2023-06-26 0:47 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-31 11:00 [PATCH v8 0/5] perf: CXL 3.0 Performance Monitoring Unit support Jonathan Cameron
2023-05-31 11:00 ` [PATCH v8 1/5] perf: Allow a PMU to have a parent Jonathan Cameron
2023-05-31 11:00 ` [PATCH v8 2/5] cxl: Add functions to get an instance of / count regblocks of a given type Jonathan Cameron
2023-05-31 11:00 ` [PATCH v8 3/5] cxl/pci: Find and register CXL PMU devices Jonathan Cameron
2023-06-26 0:46 ` Dan Williams [this message]
2023-05-31 11:00 ` [PATCH v8 4/5] perf: CXL Performance Monitoring Unit driver Jonathan Cameron
2023-05-31 18:00 ` Namhyung Kim
2023-05-31 11:00 ` [PATCH v8 5/5] docs: perf: Minimal introduction the the CXL PMU device and driver Jonathan Cameron
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