* [Patch v7 01/12] perf/x86: Remove redundant is_x86_event() prototype
2025-08-28 1:34 [Patch v7 00/12] arch-PEBS enabling for Intel platforms Dapeng Mi
@ 2025-08-28 1:34 ` Dapeng Mi
2025-08-28 1:34 ` [Patch v7 02/12] perf/x86/intel: Fix NULL event access and potential PEBS record loss Dapeng Mi
` (12 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Dapeng Mi @ 2025-08-28 1:34 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Kan Liang, Andi Kleen, Eranian Stephane
Cc: linux-kernel, linux-perf-users, Dapeng Mi, Dapeng Mi
2 is_x86_event() prototypes are defined in perf_event.h. Remove the
redundant one.
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/perf_event.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 2b969386dcdd..285779c73479 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -1124,7 +1124,6 @@ static struct perf_pmu_format_hybrid_attr format_attr_hybrid_##_name = {\
.pmu_type = _pmu, \
}
-int is_x86_event(struct perf_event *event);
struct pmu *x86_get_pmu(unsigned int cpu);
extern struct x86_pmu x86_pmu __read_mostly;
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [Patch v7 02/12] perf/x86/intel: Fix NULL event access and potential PEBS record loss
2025-08-28 1:34 [Patch v7 00/12] arch-PEBS enabling for Intel platforms Dapeng Mi
2025-08-28 1:34 ` [Patch v7 01/12] perf/x86: Remove redundant is_x86_event() prototype Dapeng Mi
@ 2025-08-28 1:34 ` Dapeng Mi
2025-09-08 8:43 ` kernel test robot
2025-08-28 1:34 ` [Patch v7 03/12] perf/x86/intel: Replace x86_pmu.drain_pebs calling with static call Dapeng Mi
` (11 subsequent siblings)
13 siblings, 1 reply; 22+ messages in thread
From: Dapeng Mi @ 2025-08-28 1:34 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Kan Liang, Andi Kleen, Eranian Stephane
Cc: linux-kernel, linux-perf-users, Dapeng Mi, Dapeng Mi,
kernel test robot
When intel_pmu_drain_pebs_icl() is called to drain PEBS records, the
perf_event_overflow() could be called to process the last PEBS record.
While perf_event_overflow() could trigger the interrupt throttle and
stop all events of the group, like what the below call-chain shows.
perf_event_overflow()
-> __perf_event_overflow()
->__perf_event_account_interrupt()
-> perf_event_throttle_group()
-> perf_event_throttle()
-> event->pmu->stop()
-> x86_pmu_stop()
The side effect of stopping the events is that all corresponding event
pointers in cpuc->events[] array are cleared to NULL.
Assume there are two PEBS events (event a and event b) in a group. When
intel_pmu_drain_pebs_icl() calls perf_event_overflow() to process the
last PEBS record of PEBS event a, interrupt throttle is triggered and
all pointers of event a and event b are cleared to NULL. Then
intel_pmu_drain_pebs_icl() tries to process the last PEBS record of
event b and encounters NULL pointer access.
To avoid this NULL event access and potential PEBS record loss, snapshot
cpuc->events[] into a local events[] before drian_pebs() helper calling
perf_event_overflow() and then use the local events[] to process the
left PEBS records.
Besides intel_pmu_drain_pebs_nhm() has similar issue and fix it as well.
Reported-by: kernel test robot <oliver.sang@intel.com>
Closes: https://lore.kernel.org/oe-lkp/202507042103.a15d2923-lkp@intel.com
Fixes: 9734e25fbf5a ("perf: Fix the throttle logic for a group")
Suggested-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/intel/ds.c | 25 +++++++++++++++++++++++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index c0b7ac1c7594..b71973e140c2 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -2487,6 +2487,7 @@ static void intel_pmu_pebs_event_update_no_drain(struct cpu_hw_events *cpuc, u64
static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_data *data)
{
+ struct perf_event *events[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {NULL};
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
struct debug_store *ds = cpuc->ds;
struct perf_event *event;
@@ -2572,13 +2573,22 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_d
}
counts[bit]++;
+ /*
+ * perf_event_overflow() called by below __intel_pmu_pebs_events()
+ * could trigger interrupt throttle and clear all event pointers of
+ * the group in cpuc->events[] to NULL. So snapshot the event[] before
+ * it could be cleared. This avoids the possible NULL event pointer
+ * access and PEBS record loss.
+ */
+ if (counts[bit] && !events[bit])
+ events[bit] = cpuc->events[bit];
}
for_each_set_bit(bit, (unsigned long *)&mask, size) {
if ((counts[bit] == 0) && (error[bit] == 0))
continue;
- event = cpuc->events[bit];
+ event = events[bit];
if (WARN_ON_ONCE(!event))
continue;
@@ -2603,6 +2613,7 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_d
static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_data *data)
{
+ struct perf_event *events[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {NULL};
short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
void *last[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS];
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
@@ -2655,6 +2666,16 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_d
setup_pebs_adaptive_sample_data);
}
last[bit] = at;
+
+ /*
+ * perf_event_overflow() called by below __intel_pmu_pebs_last_event()
+ * could trigger interrupt throttle and clear all event pointers of
+ * the group in cpuc->events[] to NULL. So snapshot the event[] before
+ * it could be cleared. This avoids the possible NULL event pointer
+ * access and PEBS record loss.
+ */
+ if (counts[bit] && !events[bit])
+ events[bit] = cpuc->events[bit];
}
}
@@ -2662,7 +2683,7 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_d
if (!counts[bit])
continue;
- event = cpuc->events[bit];
+ event = events[bit];
__intel_pmu_pebs_last_event(event, iregs, regs, data, last[bit],
counts[bit], setup_pebs_adaptive_sample_data);
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [Patch v7 02/12] perf/x86/intel: Fix NULL event access and potential PEBS record loss
2025-08-28 1:34 ` [Patch v7 02/12] perf/x86/intel: Fix NULL event access and potential PEBS record loss Dapeng Mi
@ 2025-09-08 8:43 ` kernel test robot
2025-09-08 9:05 ` Mi, Dapeng
0 siblings, 1 reply; 22+ messages in thread
From: kernel test robot @ 2025-09-08 8:43 UTC (permalink / raw)
To: Dapeng Mi
Cc: oe-lkp, lkp, kernel test robot, Kan Liang, linux-perf-users,
linux-kernel, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Namhyung Kim, Ian Rogers, Adrian Hunter,
Alexander Shishkin, Andi Kleen, Eranian Stephane, Dapeng Mi,
Dapeng Mi
[-- Attachment #1: Type: text/plain, Size: 7580 bytes --]
Hello,
kernel test robot noticed "WARNING:at_arch/x86/events/intel/ds.c:#intel_pmu_drain_pebs_nhm" on:
commit: a7138973beb1d124386472663cf50a571a2059ce ("[Patch v7 02/12] perf/x86/intel: Fix NULL event access and potential PEBS record loss")
url: https://github.com/intel-lab-lkp/linux/commits/Dapeng-Mi/perf-x86-Remove-redundant-is_x86_event-prototype/20250828-094117
patch link: https://lore.kernel.org/all/20250828013435.1528459-3-dapeng1.mi@linux.intel.com/
patch subject: [Patch v7 02/12] perf/x86/intel: Fix NULL event access and potential PEBS record loss
in testcase: phoronix-test-suite
version:
with following parameters:
test: stress-ng-1.11.0
option_a: Socket Activity
cpufreq_governor: performance
config: x86_64-rhel-9.4
compiler: gcc-12
test machine: 96 threads 2 sockets Intel(R) Xeon(R) Gold 6252 CPU @ 2.10GHz (Cascade Lake) with 512G memory
(please refer to attached dmesg/kmsg for entire log/backtrace)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <oliver.sang@intel.com>
| Closes: https://lore.kernel.org/oe-lkp/202509081646.d101cfb7-lkp@intel.com
The kernel config and materials to reproduce are available at:
https://download.01.org/0day-ci/archive/20250908/202509081646.d101cfb7-lkp@intel.com
the dmesg in above link is not very clear, so we also attached one dmesg FYI,
from which:
[ 41.225784][ C82] ------------[ cut here ]------------
[ 41.225786][ C82] WARNING: CPU: 82 PID: 3704 at arch/x86/events/intel/ds.c:2592 intel_pmu_drain_pebs_nhm+0x56b/0x630
[ 41.225791][ C82] Modules linked in: xt_conntrack nft_chain_nat xt_MASQUERADE nf_nat nf_conntrack_netlink nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4
xt_addrtype nft_compat nf_tables nfnetlink br_netfilter bridge stp llc dm_thin_pool dm_persistent_data dm_bio_prison dm_bufio qrtr sg binfmt_misc loop fus
e dm_mod overlay btrfs blake2b_generic xor raid6_pq intel_rapl_msr intel_rapl_common intel_uncore_frequency intel_uncore_frequency_common skx_edac skx_eda
c_common nfit libnvdimm x86_pkg_temp_thermal intel_powerclamp coretemp kvm_intel kvm irdma sd_mod ast irqbypass ice ipmi_ssif drm_client_lib snd_pcm ghash
_clmulni_intel drm_shmem_helper snd_timer gnss rapl drm_kms_helper intel_cstate snd ahci ib_uverbs libahci mei_me soundcore acpi_power_meter i2c_i801 ioat
dma drm ib_core pcspkr intel_uncore ipmi_si acpi_ipmi libata mei joydev i2c_smbus intel_pch_thermal lpc_ich dca wmi ipmi_devintf ipmi_msghandler acpi_pad
[ 41.225831][ C82] CPU: 82 UID: 0 PID: 3704 Comm: sleep Tainted: G S 6.17.0-rc1-00052-ga7138973beb1 #1 VOLUNTARY
[ 41.225834][ C82] Tainted: [S]=CPU_OUT_OF_SPEC
[ 41.225835][ C82] Hardware name: Intel Corporation S2600WFT/S2600WFT, BIOS SE5C620.86B.02.01.0008.031920191559 03/19/2019
[ 41.225836][ C82] RIP: 0010:intel_pmu_drain_pebs_nhm+0x56b/0x630
[ 41.225839][ C82] Code: 48 e8 b9 cd fe ff 85 c0 0f 84 a9 00 00 00 41 f6 84 24 a4 01 00 00 80 0f 84 9a 00 00 00 4c 89 ef e8 1a 2a 34 00 e9 c7 fc ff ff
<0f> 0b e9 c0 fc ff ff 0f 0b e9 b9 fc ff ff 48 8b 04 cb 48 89 84 cc
[ 41.225841][ C82] RSP: 0018:fffffe00012f38c0 EFLAGS: 00010046
[ 41.225843][ C82] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000000000
[ 41.225844][ C82] RDX: 0000000000000001 RSI: 0000000000000004 RDI: fffffe00012f3900
[ 41.225845][ C82] RBP: fffffe00013120c8 R08: 0000000000000000 R09: 0000000000000000
[ 20.931889][ T1340] Error: Driver 'pcspkr' is already registered, aborting...
[ 41.225846][ C82] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000000
[ 41.225847][ C82] R13: 0000000000000000 R14: fffffe00012f3c80 R15: 0000000000000000
[ 41.225848][ C82] FS: 0000000000000000(0000) GS:ffff88f027c62000(0000) knlGS:0000000000000000
[ 21.006859][ T1512] sd 6:0:0:0: Attached scsi generic sg0 type 0
[ 21.013583][ T1512] sd 7:0:0:0: Attached scsi generic sg1 type 0
[ 41.225849][ C82] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 41.225851][ C82] CR2: 00007ffe5571fe7c CR3: 00000040c5ae1003 CR4: 00000000007726f0
[ 41.225852][ C82] PKRU: 55555554
[ 41.225853][ C82] Call Trace:
[ 41.225855][ C82] <NMI>
[ 41.225861][ C82] handle_pmi_common+0x29b/0x430
[ 41.225865][ C82] intel_pmu_handle_irq+0x109/0x2b0
[ 41.225867][ C82] perf_event_nmi_handler+0x2a/0x70
[ 41.225870][ C82] nmi_handle+0x53/0x130
[ 41.225873][ C82] default_do_nmi+0x11d/0x170
[ 41.225876][ C82] exc_nmi+0x106/0x1b0
[ 41.225878][ C82] end_repeat_nmi+0xf/0x53
[ 41.225880][ C82] RIP: 0010:find_next_fd+0x2a/0xb0
[ 41.225883][ C82] Code: 0f 1f 44 00 00 41 54 89 f2 48 c7 c0 ff ff ff ff 49 89 fc 55 c1 ea 06 53 89 f3 48 8b 77 18 89 d9 48 d3 e0 48 f7 d0 48 0b 04 d6
<48> 83 f8 ff 74 0d 48 f7 d0 f3 48 0f bc c0 83 f8 3f 76 3a 41 8b 2c
[ 41.225885][ C82] RSP: 0018:ffffc90025283b90 EFLAGS: 00000206
[ 41.225886][ C82] RAX: 0000000000000017 RBX: 0000000000000003 RCX: 0000000000000003
[ 41.225887][ C82] RDX: 0000000000000000 RSI: ffff88f06d277150 RDI: ffff88f06d2770e8
[ 41.225888][ C82] RBP: 0000000000000400 R08: 8080808080808080 R09: 979c8d9e9a8cdfff
[ 41.225889][ C82] R10: fefefefefefefeff R11: 0000000000000000 R12: ffff88f06d2770e8
[ 41.225890][ C82] R13: 0000000000088000 R14: ffff88f06d2770c0 R15: ffff88f06d2770e8
[ 41.225893][ C82] ? find_next_fd+0x2a/0xb0
[ 41.225896][ C82] ? find_next_fd+0x2a/0xb0
[ 41.225899][ C82] </NMI>
[ 41.225899][ C82] <TASK>
[ 41.225900][ C82] alloc_fd+0x55/0x130
[ 41.225902][ C82] do_sys_openat2+0x5a/0xf0
[ 41.225905][ C82] __x64_sys_openat+0x6d/0xb0
[ 41.225907][ C82] do_syscall_64+0x7f/0x2b0
[ 41.225909][ C82] ? vfs_statx+0x68/0x170
[ 41.225911][ C82] ? strncpy_from_user+0x26/0xf0
[ 41.225914][ C82] ? vfs_fstatat+0x75/0xb0
[ 41.225917][ C82] ? __do_sys_newfstatat+0x25/0x70
[ 41.225919][ C82] ? path_openat+0xb6/0x2b0
[ 41.225921][ C82] ? do_syscall_64+0x7f/0x2b0
[ 41.225922][ C82] ? do_filp_open+0xc3/0x170
[ 41.225924][ C82] ? do_syscall_64+0x7f/0x2b0
[ 41.225925][ C82] ? __cond_resched+0x1e/0x70
[ 41.225928][ C82] ? check_heap_object+0x34/0x1b0
[ 41.225931][ C82] ? __check_object_size+0x5c/0x130
[ 41.225933][ C82] ? do_sys_openat2+0x8a/0xf0
[ 41.225936][ C82] ? __x64_sys_openat+0x6d/0xb0
[ 41.225938][ C82] ? clear_bhb_loop+0x30/0x80
[ 41.225940][ C82] ? clear_bhb_loop+0x30/0x80
[ 41.225942][ C82] entry_SYSCALL_64_after_hwframe+0x76/0x7e
[ 41.225944][ C82] RIP: 0033:0x7eff04bb9a2d
[ 41.225946][ C82] Code: 48 89 54 24 e0 41 83 e2 40 75 32 89 f0 25 00 00 41 00 3d 00 00 41 00 74 24 89 f2 b8 01 01 00 00 48 89 fe bf 9c ff ff ff 0f 05
<48> 3d 00 f0 ff ff 77 33 c3 66 2e 0f 1f 84 00 00 00 00 00 48 8d 44
[ 41.225947][ C82] RSP: 002b:00007ffe5571f7e8 EFLAGS: 00000287 ORIG_RAX: 0000000000000101
[ 41.225949][ C82] RAX: ffffffffffffffda RBX: 0000558b3236dbe6 RCX: 00007eff04bb9a2d
[ 41.225950][ C82] RDX: 0000000000080000 RSI: 00007eff04bc20b1 RDI: 00000000ffffff9c
[ 41.225951][ C82] RBP: 00007eff04bcd1f8 R08: 0000000000000000 R09: 0000558b3236dbe6
[ 41.225952][ C82] R10: 0000000000000000 R11: 0000000000000287 R12: ffffffffffffffff
[ 41.225953][ C82] R13: 0000000000000001 R14: 00007eff04bcc020 R15: 00007eff04bcd6b8
[ 41.225954][ C82] </TASK>
[ 41.225955][ C82] ---[ end trace 0000000000000000 ]---
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
[-- Attachment #2: dmesg-a7138973be.xz --]
[-- Type: application/x-xz, Size: 48556 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [Patch v7 02/12] perf/x86/intel: Fix NULL event access and potential PEBS record loss
2025-09-08 8:43 ` kernel test robot
@ 2025-09-08 9:05 ` Mi, Dapeng
2025-09-28 6:00 ` Mi, Dapeng
0 siblings, 1 reply; 22+ messages in thread
From: Mi, Dapeng @ 2025-09-08 9:05 UTC (permalink / raw)
To: kernel test robot
Cc: oe-lkp, lkp, Kan Liang, linux-perf-users, linux-kernel,
Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Andi Kleen, Eranian Stephane, Dapeng Mi
On 9/8/2025 4:43 PM, kernel test robot wrote:
> Hello,
>
> kernel test robot noticed "WARNING:at_arch/x86/events/intel/ds.c:#intel_pmu_drain_pebs_nhm" on:
>
> commit: a7138973beb1d124386472663cf50a571a2059ce ("[Patch v7 02/12] perf/x86/intel: Fix NULL event access and potential PEBS record loss")
> url: https://github.com/intel-lab-lkp/linux/commits/Dapeng-Mi/perf-x86-Remove-redundant-is_x86_event-prototype/20250828-094117
> patch link: https://lore.kernel.org/all/20250828013435.1528459-3-dapeng1.mi@linux.intel.com/
> patch subject: [Patch v7 02/12] perf/x86/intel: Fix NULL event access and potential PEBS record loss
>
> in testcase: phoronix-test-suite
> version:
> with following parameters:
>
> test: stress-ng-1.11.0
> option_a: Socket Activity
> cpufreq_governor: performance
>
>
>
> config: x86_64-rhel-9.4
> compiler: gcc-12
> test machine: 96 threads 2 sockets Intel(R) Xeon(R) Gold 6252 CPU @ 2.10GHz (Cascade Lake) with 512G memory
>
> (please refer to attached dmesg/kmsg for entire log/backtrace)
>
>
>
> If you fix the issue in a separate patch/commit (i.e. not just a new version of
> the same patch/commit), kindly add following tags
> | Reported-by: kernel test robot <oliver.sang@intel.com>
> | Closes: https://lore.kernel.org/oe-lkp/202509081646.d101cfb7-lkp@intel.com
>
>
>
> The kernel config and materials to reproduce are available at:
> https://download.01.org/0day-ci/archive/20250908/202509081646.d101cfb7-lkp@intel.com
>
>
> the dmesg in above link is not very clear, so we also attached one dmesg FYI,
> from which:
>
> [ 41.225784][ C82] ------------[ cut here ]------------
> [ 41.225786][ C82] WARNING: CPU: 82 PID: 3704 at arch/x86/events/intel/ds.c:2592 intel_pmu_drain_pebs_nhm+0x56b/0x630
> [ 41.225791][ C82] Modules linked in: xt_conntrack nft_chain_nat xt_MASQUERADE nf_nat nf_conntrack_netlink nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4
> xt_addrtype nft_compat nf_tables nfnetlink br_netfilter bridge stp llc dm_thin_pool dm_persistent_data dm_bio_prison dm_bufio qrtr sg binfmt_misc loop fus
> e dm_mod overlay btrfs blake2b_generic xor raid6_pq intel_rapl_msr intel_rapl_common intel_uncore_frequency intel_uncore_frequency_common skx_edac skx_eda
> c_common nfit libnvdimm x86_pkg_temp_thermal intel_powerclamp coretemp kvm_intel kvm irdma sd_mod ast irqbypass ice ipmi_ssif drm_client_lib snd_pcm ghash
> _clmulni_intel drm_shmem_helper snd_timer gnss rapl drm_kms_helper intel_cstate snd ahci ib_uverbs libahci mei_me soundcore acpi_power_meter i2c_i801 ioat
> dma drm ib_core pcspkr intel_uncore ipmi_si acpi_ipmi libata mei joydev i2c_smbus intel_pch_thermal lpc_ich dca wmi ipmi_devintf ipmi_msghandler acpi_pad
> [ 41.225831][ C82] CPU: 82 UID: 0 PID: 3704 Comm: sleep Tainted: G S 6.17.0-rc1-00052-ga7138973beb1 #1 VOLUNTARY
> [ 41.225834][ C82] Tainted: [S]=CPU_OUT_OF_SPEC
> [ 41.225835][ C82] Hardware name: Intel Corporation S2600WFT/S2600WFT, BIOS SE5C620.86B.02.01.0008.031920191559 03/19/2019
> [ 41.225836][ C82] RIP: 0010:intel_pmu_drain_pebs_nhm+0x56b/0x630
> [ 41.225839][ C82] Code: 48 e8 b9 cd fe ff 85 c0 0f 84 a9 00 00 00 41 f6 84 24 a4 01 00 00 80 0f 84 9a 00 00 00 4c 89 ef e8 1a 2a 34 00 e9 c7 fc ff ff
> <0f> 0b e9 c0 fc ff ff 0f 0b e9 b9 fc ff ff 48 8b 04 cb 48 89 84 cc
> [ 41.225841][ C82] RSP: 0018:fffffe00012f38c0 EFLAGS: 00010046
> [ 41.225843][ C82] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000000000
> [ 41.225844][ C82] RDX: 0000000000000001 RSI: 0000000000000004 RDI: fffffe00012f3900
> [ 41.225845][ C82] RBP: fffffe00013120c8 R08: 0000000000000000 R09: 0000000000000000
> [ 20.931889][ T1340] Error: Driver 'pcspkr' is already registered, aborting...
> [ 41.225846][ C82] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000000
> [ 41.225847][ C82] R13: 0000000000000000 R14: fffffe00012f3c80 R15: 0000000000000000
> [ 41.225848][ C82] FS: 0000000000000000(0000) GS:ffff88f027c62000(0000) knlGS:0000000000000000
> [ 21.006859][ T1512] sd 6:0:0:0: Attached scsi generic sg0 type 0
> [ 21.013583][ T1512] sd 7:0:0:0: Attached scsi generic sg1 type 0
> [ 41.225849][ C82] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> [ 41.225851][ C82] CR2: 00007ffe5571fe7c CR3: 00000040c5ae1003 CR4: 00000000007726f0
> [ 41.225852][ C82] PKRU: 55555554
> [ 41.225853][ C82] Call Trace:
> [ 41.225855][ C82] <NMI>
> [ 41.225861][ C82] handle_pmi_common+0x29b/0x430
> [ 41.225865][ C82] intel_pmu_handle_irq+0x109/0x2b0
> [ 41.225867][ C82] perf_event_nmi_handler+0x2a/0x70
> [ 41.225870][ C82] nmi_handle+0x53/0x130
> [ 41.225873][ C82] default_do_nmi+0x11d/0x170
> [ 41.225876][ C82] exc_nmi+0x106/0x1b0
> [ 41.225878][ C82] end_repeat_nmi+0xf/0x53
> [ 41.225880][ C82] RIP: 0010:find_next_fd+0x2a/0xb0
> [ 41.225883][ C82] Code: 0f 1f 44 00 00 41 54 89 f2 48 c7 c0 ff ff ff ff 49 89 fc 55 c1 ea 06 53 89 f3 48 8b 77 18 89 d9 48 d3 e0 48 f7 d0 48 0b 04 d6
> <48> 83 f8 ff 74 0d 48 f7 d0 f3 48 0f bc c0 83 f8 3f 76 3a 41 8b 2c
> [ 41.225885][ C82] RSP: 0018:ffffc90025283b90 EFLAGS: 00000206
> [ 41.225886][ C82] RAX: 0000000000000017 RBX: 0000000000000003 RCX: 0000000000000003
> [ 41.225887][ C82] RDX: 0000000000000000 RSI: ffff88f06d277150 RDI: ffff88f06d2770e8
> [ 41.225888][ C82] RBP: 0000000000000400 R08: 8080808080808080 R09: 979c8d9e9a8cdfff
> [ 41.225889][ C82] R10: fefefefefefefeff R11: 0000000000000000 R12: ffff88f06d2770e8
> [ 41.225890][ C82] R13: 0000000000088000 R14: ffff88f06d2770c0 R15: ffff88f06d2770e8
> [ 41.225893][ C82] ? find_next_fd+0x2a/0xb0
> [ 41.225896][ C82] ? find_next_fd+0x2a/0xb0
> [ 41.225899][ C82] </NMI>
> [ 41.225899][ C82] <TASK>
> [ 41.225900][ C82] alloc_fd+0x55/0x130
> [ 41.225902][ C82] do_sys_openat2+0x5a/0xf0
> [ 41.225905][ C82] __x64_sys_openat+0x6d/0xb0
> [ 41.225907][ C82] do_syscall_64+0x7f/0x2b0
> [ 41.225909][ C82] ? vfs_statx+0x68/0x170
> [ 41.225911][ C82] ? strncpy_from_user+0x26/0xf0
> [ 41.225914][ C82] ? vfs_fstatat+0x75/0xb0
> [ 41.225917][ C82] ? __do_sys_newfstatat+0x25/0x70
> [ 41.225919][ C82] ? path_openat+0xb6/0x2b0
> [ 41.225921][ C82] ? do_syscall_64+0x7f/0x2b0
> [ 41.225922][ C82] ? do_filp_open+0xc3/0x170
> [ 41.225924][ C82] ? do_syscall_64+0x7f/0x2b0
> [ 41.225925][ C82] ? __cond_resched+0x1e/0x70
> [ 41.225928][ C82] ? check_heap_object+0x34/0x1b0
> [ 41.225931][ C82] ? __check_object_size+0x5c/0x130
> [ 41.225933][ C82] ? do_sys_openat2+0x8a/0xf0
> [ 41.225936][ C82] ? __x64_sys_openat+0x6d/0xb0
> [ 41.225938][ C82] ? clear_bhb_loop+0x30/0x80
> [ 41.225940][ C82] ? clear_bhb_loop+0x30/0x80
> [ 41.225942][ C82] entry_SYSCALL_64_after_hwframe+0x76/0x7e
> [ 41.225944][ C82] RIP: 0033:0x7eff04bb9a2d
> [ 41.225946][ C82] Code: 48 89 54 24 e0 41 83 e2 40 75 32 89 f0 25 00 00 41 00 3d 00 00 41 00 74 24 89 f2 b8 01 01 00 00 48 89 fe bf 9c ff ff ff 0f 05
> <48> 3d 00 f0 ff ff 77 33 c3 66 2e 0f 1f 84 00 00 00 00 00 48 8d 44
> [ 41.225947][ C82] RSP: 002b:00007ffe5571f7e8 EFLAGS: 00000287 ORIG_RAX: 0000000000000101
> [ 41.225949][ C82] RAX: ffffffffffffffda RBX: 0000558b3236dbe6 RCX: 00007eff04bb9a2d
> [ 41.225950][ C82] RDX: 0000000000080000 RSI: 00007eff04bc20b1 RDI: 00000000ffffff9c
> [ 41.225951][ C82] RBP: 00007eff04bcd1f8 R08: 0000000000000000 R09: 0000558b3236dbe6
> [ 41.225952][ C82] R10: 0000000000000000 R11: 0000000000000287 R12: ffffffffffffffff
> [ 41.225953][ C82] R13: 0000000000000001 R14: 00007eff04bcc020 R15: 00007eff04bcd6b8
> [ 41.225954][ C82] </TASK>
> [ 41.225955][ C82] ---[ end trace 0000000000000000 ]---
>
>
It looks the warning is triggered in the "error[i] != 0" case and lead to
the local events[] array is not initialized. Would fix it in next version.
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [Patch v7 02/12] perf/x86/intel: Fix NULL event access and potential PEBS record loss
2025-09-08 9:05 ` Mi, Dapeng
@ 2025-09-28 6:00 ` Mi, Dapeng
2025-09-30 5:19 ` Oliver Sang
0 siblings, 1 reply; 22+ messages in thread
From: Mi, Dapeng @ 2025-09-28 6:00 UTC (permalink / raw)
To: kernel test robot
Cc: oe-lkp, lkp, Kan Liang, linux-perf-users, linux-kernel,
Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Andi Kleen, Eranian Stephane, Dapeng Mi
[-- Attachment #1: Type: text/plain, Size: 9245 bytes --]
Hi Oliver,
Could you please help to validate the attached patch? The patch should fix
this warning. (Please apply this patch on top of the whole patch series).
Thanks.
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 65908880f424..ef32714cb182 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -2821,8 +2821,11 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs
*iregs, struct perf_sample_d
* If collision happened, the record will be dropped.
*/
if (pebs_status != (1ULL << bit)) {
- for_each_set_bit(i, (unsigned long *)&pebs_status,
size)
+ for_each_set_bit(i, (unsigned long *)&pebs_status,
size) {
error[i]++;
+ if (error[i] && !events[i])
+ events[i] = cpuc->events[i];
+ }
continue;
}
On 9/8/2025 5:05 PM, Mi, Dapeng wrote:
> On 9/8/2025 4:43 PM, kernel test robot wrote:
>> Hello,
>>
>> kernel test robot noticed "WARNING:at_arch/x86/events/intel/ds.c:#intel_pmu_drain_pebs_nhm" on:
>>
>> commit: a7138973beb1d124386472663cf50a571a2059ce ("[Patch v7 02/12] perf/x86/intel: Fix NULL event access and potential PEBS record loss")
>> url: https://github.com/intel-lab-lkp/linux/commits/Dapeng-Mi/perf-x86-Remove-redundant-is_x86_event-prototype/20250828-094117
>> patch link: https://lore.kernel.org/all/20250828013435.1528459-3-dapeng1.mi@linux.intel.com/
>> patch subject: [Patch v7 02/12] perf/x86/intel: Fix NULL event access and potential PEBS record loss
>>
>> in testcase: phoronix-test-suite
>> version:
>> with following parameters:
>>
>> test: stress-ng-1.11.0
>> option_a: Socket Activity
>> cpufreq_governor: performance
>>
>>
>>
>> config: x86_64-rhel-9.4
>> compiler: gcc-12
>> test machine: 96 threads 2 sockets Intel(R) Xeon(R) Gold 6252 CPU @ 2.10GHz (Cascade Lake) with 512G memory
>>
>> (please refer to attached dmesg/kmsg for entire log/backtrace)
>>
>>
>>
>> If you fix the issue in a separate patch/commit (i.e. not just a new version of
>> the same patch/commit), kindly add following tags
>> | Reported-by: kernel test robot <oliver.sang@intel.com>
>> | Closes: https://lore.kernel.org/oe-lkp/202509081646.d101cfb7-lkp@intel.com
>>
>>
>>
>> The kernel config and materials to reproduce are available at:
>> https://download.01.org/0day-ci/archive/20250908/202509081646.d101cfb7-lkp@intel.com
>>
>>
>> the dmesg in above link is not very clear, so we also attached one dmesg FYI,
>> from which:
>>
>> [ 41.225784][ C82] ------------[ cut here ]------------
>> [ 41.225786][ C82] WARNING: CPU: 82 PID: 3704 at arch/x86/events/intel/ds.c:2592 intel_pmu_drain_pebs_nhm+0x56b/0x630
>> [ 41.225791][ C82] Modules linked in: xt_conntrack nft_chain_nat xt_MASQUERADE nf_nat nf_conntrack_netlink nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4
>> xt_addrtype nft_compat nf_tables nfnetlink br_netfilter bridge stp llc dm_thin_pool dm_persistent_data dm_bio_prison dm_bufio qrtr sg binfmt_misc loop fus
>> e dm_mod overlay btrfs blake2b_generic xor raid6_pq intel_rapl_msr intel_rapl_common intel_uncore_frequency intel_uncore_frequency_common skx_edac skx_eda
>> c_common nfit libnvdimm x86_pkg_temp_thermal intel_powerclamp coretemp kvm_intel kvm irdma sd_mod ast irqbypass ice ipmi_ssif drm_client_lib snd_pcm ghash
>> _clmulni_intel drm_shmem_helper snd_timer gnss rapl drm_kms_helper intel_cstate snd ahci ib_uverbs libahci mei_me soundcore acpi_power_meter i2c_i801 ioat
>> dma drm ib_core pcspkr intel_uncore ipmi_si acpi_ipmi libata mei joydev i2c_smbus intel_pch_thermal lpc_ich dca wmi ipmi_devintf ipmi_msghandler acpi_pad
>> [ 41.225831][ C82] CPU: 82 UID: 0 PID: 3704 Comm: sleep Tainted: G S 6.17.0-rc1-00052-ga7138973beb1 #1 VOLUNTARY
>> [ 41.225834][ C82] Tainted: [S]=CPU_OUT_OF_SPEC
>> [ 41.225835][ C82] Hardware name: Intel Corporation S2600WFT/S2600WFT, BIOS SE5C620.86B.02.01.0008.031920191559 03/19/2019
>> [ 41.225836][ C82] RIP: 0010:intel_pmu_drain_pebs_nhm+0x56b/0x630
>> [ 41.225839][ C82] Code: 48 e8 b9 cd fe ff 85 c0 0f 84 a9 00 00 00 41 f6 84 24 a4 01 00 00 80 0f 84 9a 00 00 00 4c 89 ef e8 1a 2a 34 00 e9 c7 fc ff ff
>> <0f> 0b e9 c0 fc ff ff 0f 0b e9 b9 fc ff ff 48 8b 04 cb 48 89 84 cc
>> [ 41.225841][ C82] RSP: 0018:fffffe00012f38c0 EFLAGS: 00010046
>> [ 41.225843][ C82] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000000000
>> [ 41.225844][ C82] RDX: 0000000000000001 RSI: 0000000000000004 RDI: fffffe00012f3900
>> [ 41.225845][ C82] RBP: fffffe00013120c8 R08: 0000000000000000 R09: 0000000000000000
>> [ 20.931889][ T1340] Error: Driver 'pcspkr' is already registered, aborting...
>> [ 41.225846][ C82] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000000
>> [ 41.225847][ C82] R13: 0000000000000000 R14: fffffe00012f3c80 R15: 0000000000000000
>> [ 41.225848][ C82] FS: 0000000000000000(0000) GS:ffff88f027c62000(0000) knlGS:0000000000000000
>> [ 21.006859][ T1512] sd 6:0:0:0: Attached scsi generic sg0 type 0
>> [ 21.013583][ T1512] sd 7:0:0:0: Attached scsi generic sg1 type 0
>> [ 41.225849][ C82] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>> [ 41.225851][ C82] CR2: 00007ffe5571fe7c CR3: 00000040c5ae1003 CR4: 00000000007726f0
>> [ 41.225852][ C82] PKRU: 55555554
>> [ 41.225853][ C82] Call Trace:
>> [ 41.225855][ C82] <NMI>
>> [ 41.225861][ C82] handle_pmi_common+0x29b/0x430
>> [ 41.225865][ C82] intel_pmu_handle_irq+0x109/0x2b0
>> [ 41.225867][ C82] perf_event_nmi_handler+0x2a/0x70
>> [ 41.225870][ C82] nmi_handle+0x53/0x130
>> [ 41.225873][ C82] default_do_nmi+0x11d/0x170
>> [ 41.225876][ C82] exc_nmi+0x106/0x1b0
>> [ 41.225878][ C82] end_repeat_nmi+0xf/0x53
>> [ 41.225880][ C82] RIP: 0010:find_next_fd+0x2a/0xb0
>> [ 41.225883][ C82] Code: 0f 1f 44 00 00 41 54 89 f2 48 c7 c0 ff ff ff ff 49 89 fc 55 c1 ea 06 53 89 f3 48 8b 77 18 89 d9 48 d3 e0 48 f7 d0 48 0b 04 d6
>> <48> 83 f8 ff 74 0d 48 f7 d0 f3 48 0f bc c0 83 f8 3f 76 3a 41 8b 2c
>> [ 41.225885][ C82] RSP: 0018:ffffc90025283b90 EFLAGS: 00000206
>> [ 41.225886][ C82] RAX: 0000000000000017 RBX: 0000000000000003 RCX: 0000000000000003
>> [ 41.225887][ C82] RDX: 0000000000000000 RSI: ffff88f06d277150 RDI: ffff88f06d2770e8
>> [ 41.225888][ C82] RBP: 0000000000000400 R08: 8080808080808080 R09: 979c8d9e9a8cdfff
>> [ 41.225889][ C82] R10: fefefefefefefeff R11: 0000000000000000 R12: ffff88f06d2770e8
>> [ 41.225890][ C82] R13: 0000000000088000 R14: ffff88f06d2770c0 R15: ffff88f06d2770e8
>> [ 41.225893][ C82] ? find_next_fd+0x2a/0xb0
>> [ 41.225896][ C82] ? find_next_fd+0x2a/0xb0
>> [ 41.225899][ C82] </NMI>
>> [ 41.225899][ C82] <TASK>
>> [ 41.225900][ C82] alloc_fd+0x55/0x130
>> [ 41.225902][ C82] do_sys_openat2+0x5a/0xf0
>> [ 41.225905][ C82] __x64_sys_openat+0x6d/0xb0
>> [ 41.225907][ C82] do_syscall_64+0x7f/0x2b0
>> [ 41.225909][ C82] ? vfs_statx+0x68/0x170
>> [ 41.225911][ C82] ? strncpy_from_user+0x26/0xf0
>> [ 41.225914][ C82] ? vfs_fstatat+0x75/0xb0
>> [ 41.225917][ C82] ? __do_sys_newfstatat+0x25/0x70
>> [ 41.225919][ C82] ? path_openat+0xb6/0x2b0
>> [ 41.225921][ C82] ? do_syscall_64+0x7f/0x2b0
>> [ 41.225922][ C82] ? do_filp_open+0xc3/0x170
>> [ 41.225924][ C82] ? do_syscall_64+0x7f/0x2b0
>> [ 41.225925][ C82] ? __cond_resched+0x1e/0x70
>> [ 41.225928][ C82] ? check_heap_object+0x34/0x1b0
>> [ 41.225931][ C82] ? __check_object_size+0x5c/0x130
>> [ 41.225933][ C82] ? do_sys_openat2+0x8a/0xf0
>> [ 41.225936][ C82] ? __x64_sys_openat+0x6d/0xb0
>> [ 41.225938][ C82] ? clear_bhb_loop+0x30/0x80
>> [ 41.225940][ C82] ? clear_bhb_loop+0x30/0x80
>> [ 41.225942][ C82] entry_SYSCALL_64_after_hwframe+0x76/0x7e
>> [ 41.225944][ C82] RIP: 0033:0x7eff04bb9a2d
>> [ 41.225946][ C82] Code: 48 89 54 24 e0 41 83 e2 40 75 32 89 f0 25 00 00 41 00 3d 00 00 41 00 74 24 89 f2 b8 01 01 00 00 48 89 fe bf 9c ff ff ff 0f 05
>> <48> 3d 00 f0 ff ff 77 33 c3 66 2e 0f 1f 84 00 00 00 00 00 48 8d 44
>> [ 41.225947][ C82] RSP: 002b:00007ffe5571f7e8 EFLAGS: 00000287 ORIG_RAX: 0000000000000101
>> [ 41.225949][ C82] RAX: ffffffffffffffda RBX: 0000558b3236dbe6 RCX: 00007eff04bb9a2d
>> [ 41.225950][ C82] RDX: 0000000000080000 RSI: 00007eff04bc20b1 RDI: 00000000ffffff9c
>> [ 41.225951][ C82] RBP: 00007eff04bcd1f8 R08: 0000000000000000 R09: 0000558b3236dbe6
>> [ 41.225952][ C82] R10: 0000000000000000 R11: 0000000000000287 R12: ffffffffffffffff
>> [ 41.225953][ C82] R13: 0000000000000001 R14: 00007eff04bcc020 R15: 00007eff04bcd6b8
>> [ 41.225954][ C82] </TASK>
>> [ 41.225955][ C82] ---[ end trace 0000000000000000 ]---
>>
>>
> It looks the warning is triggered in the "error[i] != 0" case and lead to
> the local events[] array is not initialized. Would fix it in next version.
>
>
>
>
[-- Attachment #2: 0001-perf-x86-intel-Fix-NULL-event-access-waring-from-tes.patch --]
[-- Type: text/plain, Size: 1110 bytes --]
From 0afc076a7836433b455c8aff15d4a3ad9631ebc2 Mon Sep 17 00:00:00 2001
From: Dapeng Mi <dapeng1.mi@linux.intel.com>
Date: Sun, 28 Sep 2025 13:50:47 +0800
Subject: [PATCH] perf/x86/intel: Fix NULL event access waring from test robot
This patch fixes the warning about
https://lore.kernel.org/all/202509081646.d101cfb7-lkp@intel.com/.
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/intel/ds.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 65908880f424..ef32714cb182 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -2821,8 +2821,11 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_d
* If collision happened, the record will be dropped.
*/
if (pebs_status != (1ULL << bit)) {
- for_each_set_bit(i, (unsigned long *)&pebs_status, size)
+ for_each_set_bit(i, (unsigned long *)&pebs_status, size) {
error[i]++;
+ if (error[i] && !events[i])
+ events[i] = cpuc->events[i];
+ }
continue;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [Patch v7 02/12] perf/x86/intel: Fix NULL event access and potential PEBS record loss
2025-09-28 6:00 ` Mi, Dapeng
@ 2025-09-30 5:19 ` Oliver Sang
2025-09-30 6:19 ` Mi, Dapeng
0 siblings, 1 reply; 22+ messages in thread
From: Oliver Sang @ 2025-09-30 5:19 UTC (permalink / raw)
To: Mi, Dapeng
Cc: oe-lkp, lkp, Kan Liang, linux-perf-users, linux-kernel,
Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Andi Kleen, Eranian Stephane, Dapeng Mi, oliver.sang
[-- Attachment #1: Type: text/plain, Size: 17458 bytes --]
hi, Dapeng,
On Sun, Sep 28, 2025 at 02:00:28PM +0800, Mi, Dapeng wrote:
> Hi Oliver,
>
> Could you please help to validate the attached patch? The patch should fix
> this warning. (Please apply this patch on top of the whole patch series).
> Thanks.
the patch doesn't fix the warning [1]. one dmesg is attached FYI.
BTW, I applied this patch on top of the patch set, and the patch set itself
is applied upon f49e1be1954248. as below.
if any problem, please let us know. thanks
* f7171f90cc3a45 perf/x86/intel: Fix NULL event access waring from test robot
* 81248d31dd384c perf/x86/intel: Add counter group support for arch-PEBS
* c4dd1608098ec0 perf/x86/intel: Setup PEBS data configuration and enable legacy groups
* de78881cd5ac79 perf/x86/intel: Update dyn_constranit base on PEBS event precise level
* f560ef321b0632 perf/x86/intel: Allocate arch-PEBS buffer and initialize PEBS_BASE MSR
* 5411e99084e21d perf/x86/intel: Process arch-PEBS records or record fragments
* d721d0d90c7b30 perf/x86/intel/ds: Factor out PEBS group processing code to functions
* 0cd78a2875e1ab perf/x86/intel/ds: Factor out PEBS record processing code to functions
* cc5755ee9b8bb2 perf/x86/intel: Initialize architectural PEBS
* 995af2a15982ff perf/x86/intel: Correct large PEBS flag check
* fa9540afb72301 perf/x86/intel: Replace x86_pmu.drain_pebs calling with static call
* a7138973beb1d1 perf/x86/intel: Fix NULL event access and potential PEBS record loss
* 0c9567b36ae6f8 perf/x86: Remove redundant is_x86_event() prototype
* f49e1be1954248 perf/x86: Print PMU counters bitmap in x86_pmu_show_pmu_cap()
commit f7171f90cc3a45627643d4eadd204e2b8f45e540
Author: Dapeng Mi <dapeng1.mi@linux.intel.com>
Date: Sun Sep 28 13:50:47 2025 +0800
perf/x86/intel: Fix NULL event access waring from test robot
This patch fixes the warning about
https://lore.kernel.org/all/202509081646.d101cfb7-lkp@intel.com/.
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 65908880f4244..ef32714cb1822 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -2821,8 +2821,11 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_d
* If collision happened, the record will be dropped.
*/
if (pebs_status != (1ULL << bit)) {
- for_each_set_bit(i, (unsigned long *)&pebs_status, size)
+ for_each_set_bit(i, (unsigned long *)&pebs_status, size) {
error[i]++;
+ if (error[i] && !events[i])
+ events[i] = cpuc->events[i];
+ }
continue;
}
[1]
[ 101.198733][ C0] ------------[ cut here ]------------
[ 101.198737][ C0] WARNING: CPU: 0 PID: 2770 at arch/x86/events/intel/ds.c:2849 intel_pmu_drain_pebs_nhm+0x589/0x630
[ 101.198758][ C0] Modules linked in: xt_conntrack nft_chain_nat xt_MASQUERADE nf_nat nf_conntrack_netlink nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4
xt_addrtype nft_compat nf_tables nfnetlink br_netfilter bridge stp llc dm_thin_pool dm_persistent_data dm_bio_prison dm_bufio qrtr sg binfmt_misc loop fus
e dm_mod overlay btrfs blake2b_generic xor raid6_pq intel_rapl_msr intel_rapl_common intel_uncore_frequency intel_uncore_frequency_common skx_edac skx_eda
c_common nfit libnvdimm x86_pkg_temp_thermal intel_powerclamp coretemp kvm_intel irdma ice kvm sd_mod ast irqbypass snd_pcm gnss ghash_clmulni_intel drm_c
lient_lib snd_timer drm_shmem_helper rapl ib_uverbs snd ipmi_ssif ahci drm_kms_helper intel_cstate soundcore libahci mei_me acpi_power_meter i2c_i801 ioat
dma intel_uncore drm ib_core pcspkr libata ipmi_si acpi_ipmi mei joydev i2c_smbus intel_pch_thermal lpc_ich dca wmi ipmi_devintf ipmi_msghandler acpi_pad
[ 101.198862][ C0] CPU: 0 UID: 0 PID: 2770 Comm: perf Tainted: G S 6.17.0-rc1-00063-gf7171f90cc3a #1 VOLUNTARY
[ 101.198871][ C0] Tainted: [S]=CPU_OUT_OF_SPEC
[ 101.198873][ C0] Hardware name: Intel Corporation S2600WFT/S2600WFT, BIOS SE5C620.86B.02.01.0008.031920191559 03/19/2019
[ 101.198877][ C0] RIP: 0010:intel_pmu_drain_pebs_nhm+0x589/0x630
[ 101.198885][ C0] Code: 48 e8 1b bd fe ff 85 c0 0f 84 a9 00 00 00 41 f6 84 24 a4 01 00 00 80 0f 84 9a 00 00 00 4c 89 ef e8 bc 29 34 00 e9 a9 fc ff ff
<0f> 0b e9 a2 fc ff ff 0f 0b e9 9b fc ff ff 48 8b 04 cb 48 89 84 cc
[ 101.198890][ C0] RSP: 0018:fffffe000000d8c0 EFLAGS: 00010046
[ 101.198895][ C0] RAX: 0000000000000001 RBX: 0000000000000001 RCX: 0000000000000001
[ 101.198898][ C0] RDX: 0000000000000001 RSI: 0000000000000004 RDI: fffffe000000d900
[ 101.198901][ C0] RBP: fffffe000002c0c8 R08: 0000000000000001 R09: 0000000000000000
[ 101.198904][ C0] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000001
[ 101.198905][ C0] R13: 0000000000000000 R14: fffffe000000dc80 R15: 0000000000000001
[ 101.198908][ C0] FS: 00007f96c7747840(0000) GS:ffff88bffb7e0000(0000) knlGS:0000000000000000
[ 101.198913][ C0] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 101.198916][ C0] CR2: 00000000004ac270 CR3: 000000021df93005 CR4: 00000000007727f0
[ 101.198920][ C0] PKRU: 55555554
[ 101.198922][ C0] Call Trace:
[ 101.198927][ C0] <NMI>
[ 101.198942][ C0] handle_pmi_common+0x2e1/0x4b0
[ 101.198965][ C0] intel_pmu_handle_irq+0x109/0x2b0
[ 101.198967][ C0] perf_event_nmi_handler+0x2a/0x70
[ 101.198974][ C0] nmi_handle+0x53/0x130
[ 101.198979][ C0] default_do_nmi+0x11d/0x170
[ 101.198988][ C0] exc_nmi+0x106/0x1b0
[ 101.198990][ C0] end_repeat_nmi+0xf/0x53
[ 101.198995][ C0] RIP: 0010:clear_bhb_loop+0x5e/0x80
[ 101.198997][ C0] Code: cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc
<b8> 05 00 00 00 eb 01 90 83 e8 01 75 f8 83 e9 01 75 bb c3 cc cc cc
[ 101.198998][ C0] RSP: 0018:ffffc90025163f30 EFLAGS: 00000002
[ 101.199000][ C0] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000000004
[ 101.199001][ C0] RDX: 0000000000000000 RSI: 0000000000000010 RDI: ffffc90025163f58
[ 101.199002][ C0] RBP: ffffc90025163f48 R08: 0000000000000000 R09: 0000000000000000
[ 101.199004][ C0] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000000
[ 101.199004][ C0] R13: 0000000000000000 R14: 0000000000000000 R15: 0000000000000000
[ 101.199007][ C0] ? clear_bhb_loop+0x5e/0x80
[ 101.199010][ C0] ? clear_bhb_loop+0x5e/0x80
[ 101.199011][ C0] </NMI>
[ 101.199012][ C0] <TASK>
[ 101.199012][ C0] ? clear_bhb_loop+0x30/0x80
[ 101.199014][ C0] ? clear_bhb_loop+0x30/0x80
[ 101.199016][ C0] ? clear_bhb_loop+0xe/0x80
[ 101.199017][ C0] ? entry_SYSCALL_64_after_hwframe+0x71/0x7e
[ 101.199020][ C0] </TASK>
[ 101.199020][ C0] ---[ end trace 0000000000000000 ]---
>
> diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
> index 65908880f424..ef32714cb182 100644
> --- a/arch/x86/events/intel/ds.c
> +++ b/arch/x86/events/intel/ds.c
> @@ -2821,8 +2821,11 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs
> *iregs, struct perf_sample_d
> * If collision happened, the record will be dropped.
> */
> if (pebs_status != (1ULL << bit)) {
> - for_each_set_bit(i, (unsigned long *)&pebs_status,
> size)
> + for_each_set_bit(i, (unsigned long *)&pebs_status,
> size) {
> error[i]++;
> + if (error[i] && !events[i])
> + events[i] = cpuc->events[i];
> + }
> continue;
> }
>
>
> On 9/8/2025 5:05 PM, Mi, Dapeng wrote:
> > On 9/8/2025 4:43 PM, kernel test robot wrote:
> >> Hello,
> >>
> >> kernel test robot noticed "WARNING:at_arch/x86/events/intel/ds.c:#intel_pmu_drain_pebs_nhm" on:
> >>
> >> commit: a7138973beb1d124386472663cf50a571a2059ce ("[Patch v7 02/12] perf/x86/intel: Fix NULL event access and potential PEBS record loss")
> >> url: https://github.com/intel-lab-lkp/linux/commits/Dapeng-Mi/perf-x86-Remove-redundant-is_x86_event-prototype/20250828-094117
> >> patch link: https://lore.kernel.org/all/20250828013435.1528459-3-dapeng1.mi@linux.intel.com/
> >> patch subject: [Patch v7 02/12] perf/x86/intel: Fix NULL event access and potential PEBS record loss
> >>
> >> in testcase: phoronix-test-suite
> >> version:
> >> with following parameters:
> >>
> >> test: stress-ng-1.11.0
> >> option_a: Socket Activity
> >> cpufreq_governor: performance
> >>
> >>
> >>
> >> config: x86_64-rhel-9.4
> >> compiler: gcc-12
> >> test machine: 96 threads 2 sockets Intel(R) Xeon(R) Gold 6252 CPU @ 2.10GHz (Cascade Lake) with 512G memory
> >>
> >> (please refer to attached dmesg/kmsg for entire log/backtrace)
> >>
> >>
> >>
> >> If you fix the issue in a separate patch/commit (i.e. not just a new version of
> >> the same patch/commit), kindly add following tags
> >> | Reported-by: kernel test robot <oliver.sang@intel.com>
> >> | Closes: https://lore.kernel.org/oe-lkp/202509081646.d101cfb7-lkp@intel.com
> >>
> >>
> >>
> >> The kernel config and materials to reproduce are available at:
> >> https://download.01.org/0day-ci/archive/20250908/202509081646.d101cfb7-lkp@intel.com
> >>
> >>
> >> the dmesg in above link is not very clear, so we also attached one dmesg FYI,
> >> from which:
> >>
> >> [ 41.225784][ C82] ------------[ cut here ]------------
> >> [ 41.225786][ C82] WARNING: CPU: 82 PID: 3704 at arch/x86/events/intel/ds.c:2592 intel_pmu_drain_pebs_nhm+0x56b/0x630
> >> [ 41.225791][ C82] Modules linked in: xt_conntrack nft_chain_nat xt_MASQUERADE nf_nat nf_conntrack_netlink nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4
> >> xt_addrtype nft_compat nf_tables nfnetlink br_netfilter bridge stp llc dm_thin_pool dm_persistent_data dm_bio_prison dm_bufio qrtr sg binfmt_misc loop fus
> >> e dm_mod overlay btrfs blake2b_generic xor raid6_pq intel_rapl_msr intel_rapl_common intel_uncore_frequency intel_uncore_frequency_common skx_edac skx_eda
> >> c_common nfit libnvdimm x86_pkg_temp_thermal intel_powerclamp coretemp kvm_intel kvm irdma sd_mod ast irqbypass ice ipmi_ssif drm_client_lib snd_pcm ghash
> >> _clmulni_intel drm_shmem_helper snd_timer gnss rapl drm_kms_helper intel_cstate snd ahci ib_uverbs libahci mei_me soundcore acpi_power_meter i2c_i801 ioat
> >> dma drm ib_core pcspkr intel_uncore ipmi_si acpi_ipmi libata mei joydev i2c_smbus intel_pch_thermal lpc_ich dca wmi ipmi_devintf ipmi_msghandler acpi_pad
> >> [ 41.225831][ C82] CPU: 82 UID: 0 PID: 3704 Comm: sleep Tainted: G S 6.17.0-rc1-00052-ga7138973beb1 #1 VOLUNTARY
> >> [ 41.225834][ C82] Tainted: [S]=CPU_OUT_OF_SPEC
> >> [ 41.225835][ C82] Hardware name: Intel Corporation S2600WFT/S2600WFT, BIOS SE5C620.86B.02.01.0008.031920191559 03/19/2019
> >> [ 41.225836][ C82] RIP: 0010:intel_pmu_drain_pebs_nhm+0x56b/0x630
> >> [ 41.225839][ C82] Code: 48 e8 b9 cd fe ff 85 c0 0f 84 a9 00 00 00 41 f6 84 24 a4 01 00 00 80 0f 84 9a 00 00 00 4c 89 ef e8 1a 2a 34 00 e9 c7 fc ff ff
> >> <0f> 0b e9 c0 fc ff ff 0f 0b e9 b9 fc ff ff 48 8b 04 cb 48 89 84 cc
> >> [ 41.225841][ C82] RSP: 0018:fffffe00012f38c0 EFLAGS: 00010046
> >> [ 41.225843][ C82] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000000000
> >> [ 41.225844][ C82] RDX: 0000000000000001 RSI: 0000000000000004 RDI: fffffe00012f3900
> >> [ 41.225845][ C82] RBP: fffffe00013120c8 R08: 0000000000000000 R09: 0000000000000000
> >> [ 20.931889][ T1340] Error: Driver 'pcspkr' is already registered, aborting...
> >> [ 41.225846][ C82] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000000
> >> [ 41.225847][ C82] R13: 0000000000000000 R14: fffffe00012f3c80 R15: 0000000000000000
> >> [ 41.225848][ C82] FS: 0000000000000000(0000) GS:ffff88f027c62000(0000) knlGS:0000000000000000
> >> [ 21.006859][ T1512] sd 6:0:0:0: Attached scsi generic sg0 type 0
> >> [ 21.013583][ T1512] sd 7:0:0:0: Attached scsi generic sg1 type 0
> >> [ 41.225849][ C82] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> >> [ 41.225851][ C82] CR2: 00007ffe5571fe7c CR3: 00000040c5ae1003 CR4: 00000000007726f0
> >> [ 41.225852][ C82] PKRU: 55555554
> >> [ 41.225853][ C82] Call Trace:
> >> [ 41.225855][ C82] <NMI>
> >> [ 41.225861][ C82] handle_pmi_common+0x29b/0x430
> >> [ 41.225865][ C82] intel_pmu_handle_irq+0x109/0x2b0
> >> [ 41.225867][ C82] perf_event_nmi_handler+0x2a/0x70
> >> [ 41.225870][ C82] nmi_handle+0x53/0x130
> >> [ 41.225873][ C82] default_do_nmi+0x11d/0x170
> >> [ 41.225876][ C82] exc_nmi+0x106/0x1b0
> >> [ 41.225878][ C82] end_repeat_nmi+0xf/0x53
> >> [ 41.225880][ C82] RIP: 0010:find_next_fd+0x2a/0xb0
> >> [ 41.225883][ C82] Code: 0f 1f 44 00 00 41 54 89 f2 48 c7 c0 ff ff ff ff 49 89 fc 55 c1 ea 06 53 89 f3 48 8b 77 18 89 d9 48 d3 e0 48 f7 d0 48 0b 04 d6
> >> <48> 83 f8 ff 74 0d 48 f7 d0 f3 48 0f bc c0 83 f8 3f 76 3a 41 8b 2c
> >> [ 41.225885][ C82] RSP: 0018:ffffc90025283b90 EFLAGS: 00000206
> >> [ 41.225886][ C82] RAX: 0000000000000017 RBX: 0000000000000003 RCX: 0000000000000003
> >> [ 41.225887][ C82] RDX: 0000000000000000 RSI: ffff88f06d277150 RDI: ffff88f06d2770e8
> >> [ 41.225888][ C82] RBP: 0000000000000400 R08: 8080808080808080 R09: 979c8d9e9a8cdfff
> >> [ 41.225889][ C82] R10: fefefefefefefeff R11: 0000000000000000 R12: ffff88f06d2770e8
> >> [ 41.225890][ C82] R13: 0000000000088000 R14: ffff88f06d2770c0 R15: ffff88f06d2770e8
> >> [ 41.225893][ C82] ? find_next_fd+0x2a/0xb0
> >> [ 41.225896][ C82] ? find_next_fd+0x2a/0xb0
> >> [ 41.225899][ C82] </NMI>
> >> [ 41.225899][ C82] <TASK>
> >> [ 41.225900][ C82] alloc_fd+0x55/0x130
> >> [ 41.225902][ C82] do_sys_openat2+0x5a/0xf0
> >> [ 41.225905][ C82] __x64_sys_openat+0x6d/0xb0
> >> [ 41.225907][ C82] do_syscall_64+0x7f/0x2b0
> >> [ 41.225909][ C82] ? vfs_statx+0x68/0x170
> >> [ 41.225911][ C82] ? strncpy_from_user+0x26/0xf0
> >> [ 41.225914][ C82] ? vfs_fstatat+0x75/0xb0
> >> [ 41.225917][ C82] ? __do_sys_newfstatat+0x25/0x70
> >> [ 41.225919][ C82] ? path_openat+0xb6/0x2b0
> >> [ 41.225921][ C82] ? do_syscall_64+0x7f/0x2b0
> >> [ 41.225922][ C82] ? do_filp_open+0xc3/0x170
> >> [ 41.225924][ C82] ? do_syscall_64+0x7f/0x2b0
> >> [ 41.225925][ C82] ? __cond_resched+0x1e/0x70
> >> [ 41.225928][ C82] ? check_heap_object+0x34/0x1b0
> >> [ 41.225931][ C82] ? __check_object_size+0x5c/0x130
> >> [ 41.225933][ C82] ? do_sys_openat2+0x8a/0xf0
> >> [ 41.225936][ C82] ? __x64_sys_openat+0x6d/0xb0
> >> [ 41.225938][ C82] ? clear_bhb_loop+0x30/0x80
> >> [ 41.225940][ C82] ? clear_bhb_loop+0x30/0x80
> >> [ 41.225942][ C82] entry_SYSCALL_64_after_hwframe+0x76/0x7e
> >> [ 41.225944][ C82] RIP: 0033:0x7eff04bb9a2d
> >> [ 41.225946][ C82] Code: 48 89 54 24 e0 41 83 e2 40 75 32 89 f0 25 00 00 41 00 3d 00 00 41 00 74 24 89 f2 b8 01 01 00 00 48 89 fe bf 9c ff ff ff 0f 05
> >> <48> 3d 00 f0 ff ff 77 33 c3 66 2e 0f 1f 84 00 00 00 00 00 48 8d 44
> >> [ 41.225947][ C82] RSP: 002b:00007ffe5571f7e8 EFLAGS: 00000287 ORIG_RAX: 0000000000000101
> >> [ 41.225949][ C82] RAX: ffffffffffffffda RBX: 0000558b3236dbe6 RCX: 00007eff04bb9a2d
> >> [ 41.225950][ C82] RDX: 0000000000080000 RSI: 00007eff04bc20b1 RDI: 00000000ffffff9c
> >> [ 41.225951][ C82] RBP: 00007eff04bcd1f8 R08: 0000000000000000 R09: 0000558b3236dbe6
> >> [ 41.225952][ C82] R10: 0000000000000000 R11: 0000000000000287 R12: ffffffffffffffff
> >> [ 41.225953][ C82] R13: 0000000000000001 R14: 00007eff04bcc020 R15: 00007eff04bcd6b8
> >> [ 41.225954][ C82] </TASK>
> >> [ 41.225955][ C82] ---[ end trace 0000000000000000 ]---
> >>
> >>
> > It looks the warning is triggered in the "error[i] != 0" case and lead to
> > the local events[] array is not initialized. Would fix it in next version.
> >
> >
> >
> >
> From 0afc076a7836433b455c8aff15d4a3ad9631ebc2 Mon Sep 17 00:00:00 2001
> From: Dapeng Mi <dapeng1.mi@linux.intel.com>
> Date: Sun, 28 Sep 2025 13:50:47 +0800
> Subject: [PATCH] perf/x86/intel: Fix NULL event access waring from test robot
>
> This patch fixes the warning about
> https://lore.kernel.org/all/202509081646.d101cfb7-lkp@intel.com/.
>
> Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
> ---
> arch/x86/events/intel/ds.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
> index 65908880f424..ef32714cb182 100644
> --- a/arch/x86/events/intel/ds.c
> +++ b/arch/x86/events/intel/ds.c
> @@ -2821,8 +2821,11 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_d
> * If collision happened, the record will be dropped.
> */
> if (pebs_status != (1ULL << bit)) {
> - for_each_set_bit(i, (unsigned long *)&pebs_status, size)
> + for_each_set_bit(i, (unsigned long *)&pebs_status, size) {
> error[i]++;
> + if (error[i] && !events[i])
> + events[i] = cpuc->events[i];
> + }
> continue;
> }
>
> --
> 2.34.1
>
[-- Attachment #2: dmesg-f7171f90cc3a45.xz --]
[-- Type: application/x-xz, Size: 33672 bytes --]
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [Patch v7 02/12] perf/x86/intel: Fix NULL event access and potential PEBS record loss
2025-09-30 5:19 ` Oliver Sang
@ 2025-09-30 6:19 ` Mi, Dapeng
2025-10-02 7:09 ` Oliver Sang
0 siblings, 1 reply; 22+ messages in thread
From: Mi, Dapeng @ 2025-09-30 6:19 UTC (permalink / raw)
To: Oliver Sang
Cc: oe-lkp, lkp, Kan Liang, linux-perf-users, linux-kernel,
Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Andi Kleen, Eranian Stephane, Dapeng Mi
[-- Attachment #1: Type: text/plain, Size: 19487 bytes --]
On 9/30/2025 1:19 PM, Oliver Sang wrote:
> hi, Dapeng,
>
> On Sun, Sep 28, 2025 at 02:00:28PM +0800, Mi, Dapeng wrote:
>> Hi Oliver,
>>
>> Could you please help to validate the attached patch? The patch should fix
>> this warning. (Please apply this patch on top of the whole patch series).
>> Thanks.
> the patch doesn't fix the warning [1]. one dmesg is attached FYI.
>
> BTW, I applied this patch on top of the patch set, and the patch set itself
> is applied upon f49e1be1954248. as below.
> if any problem, please let us know. thanks
>
> * f7171f90cc3a45 perf/x86/intel: Fix NULL event access waring from test robot
> * 81248d31dd384c perf/x86/intel: Add counter group support for arch-PEBS
> * c4dd1608098ec0 perf/x86/intel: Setup PEBS data configuration and enable legacy groups
> * de78881cd5ac79 perf/x86/intel: Update dyn_constranit base on PEBS event precise level
> * f560ef321b0632 perf/x86/intel: Allocate arch-PEBS buffer and initialize PEBS_BASE MSR
> * 5411e99084e21d perf/x86/intel: Process arch-PEBS records or record fragments
> * d721d0d90c7b30 perf/x86/intel/ds: Factor out PEBS group processing code to functions
> * 0cd78a2875e1ab perf/x86/intel/ds: Factor out PEBS record processing code to functions
> * cc5755ee9b8bb2 perf/x86/intel: Initialize architectural PEBS
> * 995af2a15982ff perf/x86/intel: Correct large PEBS flag check
> * fa9540afb72301 perf/x86/intel: Replace x86_pmu.drain_pebs calling with static call
> * a7138973beb1d1 perf/x86/intel: Fix NULL event access and potential PEBS record loss
> * 0c9567b36ae6f8 perf/x86: Remove redundant is_x86_event() prototype
> * f49e1be1954248 perf/x86: Print PMU counters bitmap in x86_pmu_show_pmu_cap()
>
> commit f7171f90cc3a45627643d4eadd204e2b8f45e540
> Author: Dapeng Mi <dapeng1.mi@linux.intel.com>
> Date: Sun Sep 28 13:50:47 2025 +0800
>
> perf/x86/intel: Fix NULL event access waring from test robot
>
> This patch fixes the warning about
> https://lore.kernel.org/all/202509081646.d101cfb7-lkp@intel.com/.
>
> Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
>
> diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
> index 65908880f4244..ef32714cb1822 100644
> --- a/arch/x86/events/intel/ds.c
> +++ b/arch/x86/events/intel/ds.c
> @@ -2821,8 +2821,11 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_d
> * If collision happened, the record will be dropped.
> */
> if (pebs_status != (1ULL << bit)) {
> - for_each_set_bit(i, (unsigned long *)&pebs_status, size)
> + for_each_set_bit(i, (unsigned long *)&pebs_status, size) {
> error[i]++;
> + if (error[i] && !events[i])
> + events[i] = cpuc->events[i];
> + }
> continue;
> }
Oops, it looks previous fix was incomplete. :(
Oliver, could you please verify the new attached patch (Please apply this
patch on top of the whole patch series)? Thanks a lot for your effort.
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 65908880f424..3dedf7a0acf6 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -2781,9 +2781,11 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs
*iregs, struct perf_sample_d
/* PEBS v3 has more accurate status bits */
if (x86_pmu.intel_cap.pebs_format >= 3) {
- for_each_set_bit(bit, (unsigned long *)&pebs_status, size)
+ for_each_set_bit(bit, (unsigned long *)&pebs_status, size) {
counts[bit]++;
-
+ if (counts[bit] && !events[bit])
+ events[bit] = cpuc->events[bit];
+ }
continue;
}
@@ -2821,8 +2823,11 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs
*iregs, struct perf_sample_d
* If collision happened, the record will be dropped.
*/
if (pebs_status != (1ULL << bit)) {
- for_each_set_bit(i, (unsigned long *)&pebs_status, size)
+ for_each_set_bit(i, (unsigned long *)&pebs_status, size) {
error[i]++;
+ if (error[i] && !events[i])
+ events[i] = cpuc->events[i];
+ }
continue;
}
>
>
>
>
> [1]
> [ 101.198733][ C0] ------------[ cut here ]------------
> [ 101.198737][ C0] WARNING: CPU: 0 PID: 2770 at arch/x86/events/intel/ds.c:2849 intel_pmu_drain_pebs_nhm+0x589/0x630
> [ 101.198758][ C0] Modules linked in: xt_conntrack nft_chain_nat xt_MASQUERADE nf_nat nf_conntrack_netlink nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4
> xt_addrtype nft_compat nf_tables nfnetlink br_netfilter bridge stp llc dm_thin_pool dm_persistent_data dm_bio_prison dm_bufio qrtr sg binfmt_misc loop fus
> e dm_mod overlay btrfs blake2b_generic xor raid6_pq intel_rapl_msr intel_rapl_common intel_uncore_frequency intel_uncore_frequency_common skx_edac skx_eda
> c_common nfit libnvdimm x86_pkg_temp_thermal intel_powerclamp coretemp kvm_intel irdma ice kvm sd_mod ast irqbypass snd_pcm gnss ghash_clmulni_intel drm_c
> lient_lib snd_timer drm_shmem_helper rapl ib_uverbs snd ipmi_ssif ahci drm_kms_helper intel_cstate soundcore libahci mei_me acpi_power_meter i2c_i801 ioat
> dma intel_uncore drm ib_core pcspkr libata ipmi_si acpi_ipmi mei joydev i2c_smbus intel_pch_thermal lpc_ich dca wmi ipmi_devintf ipmi_msghandler acpi_pad
> [ 101.198862][ C0] CPU: 0 UID: 0 PID: 2770 Comm: perf Tainted: G S 6.17.0-rc1-00063-gf7171f90cc3a #1 VOLUNTARY
> [ 101.198871][ C0] Tainted: [S]=CPU_OUT_OF_SPEC
> [ 101.198873][ C0] Hardware name: Intel Corporation S2600WFT/S2600WFT, BIOS SE5C620.86B.02.01.0008.031920191559 03/19/2019
> [ 101.198877][ C0] RIP: 0010:intel_pmu_drain_pebs_nhm+0x589/0x630
> [ 101.198885][ C0] Code: 48 e8 1b bd fe ff 85 c0 0f 84 a9 00 00 00 41 f6 84 24 a4 01 00 00 80 0f 84 9a 00 00 00 4c 89 ef e8 bc 29 34 00 e9 a9 fc ff ff
> <0f> 0b e9 a2 fc ff ff 0f 0b e9 9b fc ff ff 48 8b 04 cb 48 89 84 cc
> [ 101.198890][ C0] RSP: 0018:fffffe000000d8c0 EFLAGS: 00010046
> [ 101.198895][ C0] RAX: 0000000000000001 RBX: 0000000000000001 RCX: 0000000000000001
> [ 101.198898][ C0] RDX: 0000000000000001 RSI: 0000000000000004 RDI: fffffe000000d900
> [ 101.198901][ C0] RBP: fffffe000002c0c8 R08: 0000000000000001 R09: 0000000000000000
> [ 101.198904][ C0] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000001
> [ 101.198905][ C0] R13: 0000000000000000 R14: fffffe000000dc80 R15: 0000000000000001
> [ 101.198908][ C0] FS: 00007f96c7747840(0000) GS:ffff88bffb7e0000(0000) knlGS:0000000000000000
> [ 101.198913][ C0] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> [ 101.198916][ C0] CR2: 00000000004ac270 CR3: 000000021df93005 CR4: 00000000007727f0
> [ 101.198920][ C0] PKRU: 55555554
> [ 101.198922][ C0] Call Trace:
> [ 101.198927][ C0] <NMI>
> [ 101.198942][ C0] handle_pmi_common+0x2e1/0x4b0
> [ 101.198965][ C0] intel_pmu_handle_irq+0x109/0x2b0
> [ 101.198967][ C0] perf_event_nmi_handler+0x2a/0x70
> [ 101.198974][ C0] nmi_handle+0x53/0x130
> [ 101.198979][ C0] default_do_nmi+0x11d/0x170
> [ 101.198988][ C0] exc_nmi+0x106/0x1b0
> [ 101.198990][ C0] end_repeat_nmi+0xf/0x53
> [ 101.198995][ C0] RIP: 0010:clear_bhb_loop+0x5e/0x80
> [ 101.198997][ C0] Code: cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc
> <b8> 05 00 00 00 eb 01 90 83 e8 01 75 f8 83 e9 01 75 bb c3 cc cc cc
> [ 101.198998][ C0] RSP: 0018:ffffc90025163f30 EFLAGS: 00000002
> [ 101.199000][ C0] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000000004
> [ 101.199001][ C0] RDX: 0000000000000000 RSI: 0000000000000010 RDI: ffffc90025163f58
> [ 101.199002][ C0] RBP: ffffc90025163f48 R08: 0000000000000000 R09: 0000000000000000
> [ 101.199004][ C0] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000000
> [ 101.199004][ C0] R13: 0000000000000000 R14: 0000000000000000 R15: 0000000000000000
> [ 101.199007][ C0] ? clear_bhb_loop+0x5e/0x80
> [ 101.199010][ C0] ? clear_bhb_loop+0x5e/0x80
> [ 101.199011][ C0] </NMI>
> [ 101.199012][ C0] <TASK>
> [ 101.199012][ C0] ? clear_bhb_loop+0x30/0x80
> [ 101.199014][ C0] ? clear_bhb_loop+0x30/0x80
> [ 101.199016][ C0] ? clear_bhb_loop+0xe/0x80
> [ 101.199017][ C0] ? entry_SYSCALL_64_after_hwframe+0x71/0x7e
> [ 101.199020][ C0] </TASK>
> [ 101.199020][ C0] ---[ end trace 0000000000000000 ]---
>
>
>> diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
>> index 65908880f424..ef32714cb182 100644
>> --- a/arch/x86/events/intel/ds.c
>> +++ b/arch/x86/events/intel/ds.c
>> @@ -2821,8 +2821,11 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs
>> *iregs, struct perf_sample_d
>> * If collision happened, the record will be dropped.
>> */
>> if (pebs_status != (1ULL << bit)) {
>> - for_each_set_bit(i, (unsigned long *)&pebs_status,
>> size)
>> + for_each_set_bit(i, (unsigned long *)&pebs_status,
>> size) {
>> error[i]++;
>> + if (error[i] && !events[i])
>> + events[i] = cpuc->events[i];
>> + }
>> continue;
>> }
>>
>>
>> On 9/8/2025 5:05 PM, Mi, Dapeng wrote:
>>> On 9/8/2025 4:43 PM, kernel test robot wrote:
>>>> Hello,
>>>>
>>>> kernel test robot noticed "WARNING:at_arch/x86/events/intel/ds.c:#intel_pmu_drain_pebs_nhm" on:
>>>>
>>>> commit: a7138973beb1d124386472663cf50a571a2059ce ("[Patch v7 02/12] perf/x86/intel: Fix NULL event access and potential PEBS record loss")
>>>> url: https://github.com/intel-lab-lkp/linux/commits/Dapeng-Mi/perf-x86-Remove-redundant-is_x86_event-prototype/20250828-094117
>>>> patch link: https://lore.kernel.org/all/20250828013435.1528459-3-dapeng1.mi@linux.intel.com/
>>>> patch subject: [Patch v7 02/12] perf/x86/intel: Fix NULL event access and potential PEBS record loss
>>>>
>>>> in testcase: phoronix-test-suite
>>>> version:
>>>> with following parameters:
>>>>
>>>> test: stress-ng-1.11.0
>>>> option_a: Socket Activity
>>>> cpufreq_governor: performance
>>>>
>>>>
>>>>
>>>> config: x86_64-rhel-9.4
>>>> compiler: gcc-12
>>>> test machine: 96 threads 2 sockets Intel(R) Xeon(R) Gold 6252 CPU @ 2.10GHz (Cascade Lake) with 512G memory
>>>>
>>>> (please refer to attached dmesg/kmsg for entire log/backtrace)
>>>>
>>>>
>>>>
>>>> If you fix the issue in a separate patch/commit (i.e. not just a new version of
>>>> the same patch/commit), kindly add following tags
>>>> | Reported-by: kernel test robot <oliver.sang@intel.com>
>>>> | Closes: https://lore.kernel.org/oe-lkp/202509081646.d101cfb7-lkp@intel.com
>>>>
>>>>
>>>>
>>>> The kernel config and materials to reproduce are available at:
>>>> https://download.01.org/0day-ci/archive/20250908/202509081646.d101cfb7-lkp@intel.com
>>>>
>>>>
>>>> the dmesg in above link is not very clear, so we also attached one dmesg FYI,
>>>> from which:
>>>>
>>>> [ 41.225784][ C82] ------------[ cut here ]------------
>>>> [ 41.225786][ C82] WARNING: CPU: 82 PID: 3704 at arch/x86/events/intel/ds.c:2592 intel_pmu_drain_pebs_nhm+0x56b/0x630
>>>> [ 41.225791][ C82] Modules linked in: xt_conntrack nft_chain_nat xt_MASQUERADE nf_nat nf_conntrack_netlink nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4
>>>> xt_addrtype nft_compat nf_tables nfnetlink br_netfilter bridge stp llc dm_thin_pool dm_persistent_data dm_bio_prison dm_bufio qrtr sg binfmt_misc loop fus
>>>> e dm_mod overlay btrfs blake2b_generic xor raid6_pq intel_rapl_msr intel_rapl_common intel_uncore_frequency intel_uncore_frequency_common skx_edac skx_eda
>>>> c_common nfit libnvdimm x86_pkg_temp_thermal intel_powerclamp coretemp kvm_intel kvm irdma sd_mod ast irqbypass ice ipmi_ssif drm_client_lib snd_pcm ghash
>>>> _clmulni_intel drm_shmem_helper snd_timer gnss rapl drm_kms_helper intel_cstate snd ahci ib_uverbs libahci mei_me soundcore acpi_power_meter i2c_i801 ioat
>>>> dma drm ib_core pcspkr intel_uncore ipmi_si acpi_ipmi libata mei joydev i2c_smbus intel_pch_thermal lpc_ich dca wmi ipmi_devintf ipmi_msghandler acpi_pad
>>>> [ 41.225831][ C82] CPU: 82 UID: 0 PID: 3704 Comm: sleep Tainted: G S 6.17.0-rc1-00052-ga7138973beb1 #1 VOLUNTARY
>>>> [ 41.225834][ C82] Tainted: [S]=CPU_OUT_OF_SPEC
>>>> [ 41.225835][ C82] Hardware name: Intel Corporation S2600WFT/S2600WFT, BIOS SE5C620.86B.02.01.0008.031920191559 03/19/2019
>>>> [ 41.225836][ C82] RIP: 0010:intel_pmu_drain_pebs_nhm+0x56b/0x630
>>>> [ 41.225839][ C82] Code: 48 e8 b9 cd fe ff 85 c0 0f 84 a9 00 00 00 41 f6 84 24 a4 01 00 00 80 0f 84 9a 00 00 00 4c 89 ef e8 1a 2a 34 00 e9 c7 fc ff ff
>>>> <0f> 0b e9 c0 fc ff ff 0f 0b e9 b9 fc ff ff 48 8b 04 cb 48 89 84 cc
>>>> [ 41.225841][ C82] RSP: 0018:fffffe00012f38c0 EFLAGS: 00010046
>>>> [ 41.225843][ C82] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000000000
>>>> [ 41.225844][ C82] RDX: 0000000000000001 RSI: 0000000000000004 RDI: fffffe00012f3900
>>>> [ 41.225845][ C82] RBP: fffffe00013120c8 R08: 0000000000000000 R09: 0000000000000000
>>>> [ 20.931889][ T1340] Error: Driver 'pcspkr' is already registered, aborting...
>>>> [ 41.225846][ C82] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000000
>>>> [ 41.225847][ C82] R13: 0000000000000000 R14: fffffe00012f3c80 R15: 0000000000000000
>>>> [ 41.225848][ C82] FS: 0000000000000000(0000) GS:ffff88f027c62000(0000) knlGS:0000000000000000
>>>> [ 21.006859][ T1512] sd 6:0:0:0: Attached scsi generic sg0 type 0
>>>> [ 21.013583][ T1512] sd 7:0:0:0: Attached scsi generic sg1 type 0
>>>> [ 41.225849][ C82] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>>>> [ 41.225851][ C82] CR2: 00007ffe5571fe7c CR3: 00000040c5ae1003 CR4: 00000000007726f0
>>>> [ 41.225852][ C82] PKRU: 55555554
>>>> [ 41.225853][ C82] Call Trace:
>>>> [ 41.225855][ C82] <NMI>
>>>> [ 41.225861][ C82] handle_pmi_common+0x29b/0x430
>>>> [ 41.225865][ C82] intel_pmu_handle_irq+0x109/0x2b0
>>>> [ 41.225867][ C82] perf_event_nmi_handler+0x2a/0x70
>>>> [ 41.225870][ C82] nmi_handle+0x53/0x130
>>>> [ 41.225873][ C82] default_do_nmi+0x11d/0x170
>>>> [ 41.225876][ C82] exc_nmi+0x106/0x1b0
>>>> [ 41.225878][ C82] end_repeat_nmi+0xf/0x53
>>>> [ 41.225880][ C82] RIP: 0010:find_next_fd+0x2a/0xb0
>>>> [ 41.225883][ C82] Code: 0f 1f 44 00 00 41 54 89 f2 48 c7 c0 ff ff ff ff 49 89 fc 55 c1 ea 06 53 89 f3 48 8b 77 18 89 d9 48 d3 e0 48 f7 d0 48 0b 04 d6
>>>> <48> 83 f8 ff 74 0d 48 f7 d0 f3 48 0f bc c0 83 f8 3f 76 3a 41 8b 2c
>>>> [ 41.225885][ C82] RSP: 0018:ffffc90025283b90 EFLAGS: 00000206
>>>> [ 41.225886][ C82] RAX: 0000000000000017 RBX: 0000000000000003 RCX: 0000000000000003
>>>> [ 41.225887][ C82] RDX: 0000000000000000 RSI: ffff88f06d277150 RDI: ffff88f06d2770e8
>>>> [ 41.225888][ C82] RBP: 0000000000000400 R08: 8080808080808080 R09: 979c8d9e9a8cdfff
>>>> [ 41.225889][ C82] R10: fefefefefefefeff R11: 0000000000000000 R12: ffff88f06d2770e8
>>>> [ 41.225890][ C82] R13: 0000000000088000 R14: ffff88f06d2770c0 R15: ffff88f06d2770e8
>>>> [ 41.225893][ C82] ? find_next_fd+0x2a/0xb0
>>>> [ 41.225896][ C82] ? find_next_fd+0x2a/0xb0
>>>> [ 41.225899][ C82] </NMI>
>>>> [ 41.225899][ C82] <TASK>
>>>> [ 41.225900][ C82] alloc_fd+0x55/0x130
>>>> [ 41.225902][ C82] do_sys_openat2+0x5a/0xf0
>>>> [ 41.225905][ C82] __x64_sys_openat+0x6d/0xb0
>>>> [ 41.225907][ C82] do_syscall_64+0x7f/0x2b0
>>>> [ 41.225909][ C82] ? vfs_statx+0x68/0x170
>>>> [ 41.225911][ C82] ? strncpy_from_user+0x26/0xf0
>>>> [ 41.225914][ C82] ? vfs_fstatat+0x75/0xb0
>>>> [ 41.225917][ C82] ? __do_sys_newfstatat+0x25/0x70
>>>> [ 41.225919][ C82] ? path_openat+0xb6/0x2b0
>>>> [ 41.225921][ C82] ? do_syscall_64+0x7f/0x2b0
>>>> [ 41.225922][ C82] ? do_filp_open+0xc3/0x170
>>>> [ 41.225924][ C82] ? do_syscall_64+0x7f/0x2b0
>>>> [ 41.225925][ C82] ? __cond_resched+0x1e/0x70
>>>> [ 41.225928][ C82] ? check_heap_object+0x34/0x1b0
>>>> [ 41.225931][ C82] ? __check_object_size+0x5c/0x130
>>>> [ 41.225933][ C82] ? do_sys_openat2+0x8a/0xf0
>>>> [ 41.225936][ C82] ? __x64_sys_openat+0x6d/0xb0
>>>> [ 41.225938][ C82] ? clear_bhb_loop+0x30/0x80
>>>> [ 41.225940][ C82] ? clear_bhb_loop+0x30/0x80
>>>> [ 41.225942][ C82] entry_SYSCALL_64_after_hwframe+0x76/0x7e
>>>> [ 41.225944][ C82] RIP: 0033:0x7eff04bb9a2d
>>>> [ 41.225946][ C82] Code: 48 89 54 24 e0 41 83 e2 40 75 32 89 f0 25 00 00 41 00 3d 00 00 41 00 74 24 89 f2 b8 01 01 00 00 48 89 fe bf 9c ff ff ff 0f 05
>>>> <48> 3d 00 f0 ff ff 77 33 c3 66 2e 0f 1f 84 00 00 00 00 00 48 8d 44
>>>> [ 41.225947][ C82] RSP: 002b:00007ffe5571f7e8 EFLAGS: 00000287 ORIG_RAX: 0000000000000101
>>>> [ 41.225949][ C82] RAX: ffffffffffffffda RBX: 0000558b3236dbe6 RCX: 00007eff04bb9a2d
>>>> [ 41.225950][ C82] RDX: 0000000000080000 RSI: 00007eff04bc20b1 RDI: 00000000ffffff9c
>>>> [ 41.225951][ C82] RBP: 00007eff04bcd1f8 R08: 0000000000000000 R09: 0000558b3236dbe6
>>>> [ 41.225952][ C82] R10: 0000000000000000 R11: 0000000000000287 R12: ffffffffffffffff
>>>> [ 41.225953][ C82] R13: 0000000000000001 R14: 00007eff04bcc020 R15: 00007eff04bcd6b8
>>>> [ 41.225954][ C82] </TASK>
>>>> [ 41.225955][ C82] ---[ end trace 0000000000000000 ]---
>>>>
>>>>
>>> It looks the warning is triggered in the "error[i] != 0" case and lead to
>>> the local events[] array is not initialized. Would fix it in next version.
>>>
>>>
>>>
>>>
>> From 0afc076a7836433b455c8aff15d4a3ad9631ebc2 Mon Sep 17 00:00:00 2001
>> From: Dapeng Mi <dapeng1.mi@linux.intel.com>
>> Date: Sun, 28 Sep 2025 13:50:47 +0800
>> Subject: [PATCH] perf/x86/intel: Fix NULL event access waring from test robot
>>
>> This patch fixes the warning about
>> https://lore.kernel.org/all/202509081646.d101cfb7-lkp@intel.com/.
>>
>> Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
>> ---
>> arch/x86/events/intel/ds.c | 5 ++++-
>> 1 file changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
>> index 65908880f424..ef32714cb182 100644
>> --- a/arch/x86/events/intel/ds.c
>> +++ b/arch/x86/events/intel/ds.c
>> @@ -2821,8 +2821,11 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_d
>> * If collision happened, the record will be dropped.
>> */
>> if (pebs_status != (1ULL << bit)) {
>> - for_each_set_bit(i, (unsigned long *)&pebs_status, size)
>> + for_each_set_bit(i, (unsigned long *)&pebs_status, size) {
>> error[i]++;
>> + if (error[i] && !events[i])
>> + events[i] = cpuc->events[i];
>> + }
>> continue;
>> }
>>
>> --
>> 2.34.1
>>
[-- Attachment #2: 0001-Fixup-perf-x86-intel-Fix-NULL-event-access-waring-fr.patch --]
[-- Type: text/plain, Size: 1578 bytes --]
From b36a63375f9ea5f86a8dc392a153cc2020e73551 Mon Sep 17 00:00:00 2001
From: Dapeng Mi <dapeng1.mi@linux.intel.com>
Date: Sun, 28 Sep 2025 13:50:47 +0800
Subject: [PATCH] Fixup: perf/x86/intel: Fix NULL event access waring from test
robot
This patch fixes the warning about
https://lore.kernel.org/all/202509081646.d101cfb7-lkp@intel.com/.
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/intel/ds.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 65908880f424..3dedf7a0acf6 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -2781,9 +2781,11 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_d
/* PEBS v3 has more accurate status bits */
if (x86_pmu.intel_cap.pebs_format >= 3) {
- for_each_set_bit(bit, (unsigned long *)&pebs_status, size)
+ for_each_set_bit(bit, (unsigned long *)&pebs_status, size) {
counts[bit]++;
-
+ if (counts[bit] && !events[bit])
+ events[bit] = cpuc->events[bit];
+ }
continue;
}
@@ -2821,8 +2823,11 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_d
* If collision happened, the record will be dropped.
*/
if (pebs_status != (1ULL << bit)) {
- for_each_set_bit(i, (unsigned long *)&pebs_status, size)
+ for_each_set_bit(i, (unsigned long *)&pebs_status, size) {
error[i]++;
+ if (error[i] && !events[i])
+ events[i] = cpuc->events[i];
+ }
continue;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [Patch v7 02/12] perf/x86/intel: Fix NULL event access and potential PEBS record loss
2025-09-30 6:19 ` Mi, Dapeng
@ 2025-10-02 7:09 ` Oliver Sang
2025-10-06 8:03 ` Mi, Dapeng
0 siblings, 1 reply; 22+ messages in thread
From: Oliver Sang @ 2025-10-02 7:09 UTC (permalink / raw)
To: Mi, Dapeng
Cc: oe-lkp, lkp, Kan Liang, linux-perf-users, linux-kernel,
Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Andi Kleen, Eranian Stephane, Dapeng Mi, oliver.sang
hi, Dapeng,
On Tue, Sep 30, 2025 at 02:19:25PM +0800, Mi, Dapeng wrote:
>
[...]
>
> Oops, it looks previous fix was incomplete. :(
>
> Oliver, could you please verify the new attached patch (Please apply this
> patch on top of the whole patch series)? Thanks a lot for your effort.
we confirmed the patch fixed the warning we reported.
Tested-by: kernel test robot <oliver.sang@intel.com>
=========================================================================================
compiler/cpufreq_governor/kconfig/option_a/rootfs/tbox_group/test/testcase:
gcc-12/performance/x86_64-rhel-9.4/Socket Activity/debian-12-x86_64-phoronix/lkp-csl-2sp7/stress-ng-1.11.0/phoronix-test-suite
commit:
0c9567b36ae6f8 ("perf/x86: Remove redundant is_x86_event() prototype")
a7138973beb1d1 ("perf/x86/intel: Fix NULL event access and potential PEBS record loss")
81248d31dd384c ("perf/x86/intel: Add counter group support for arch-PEBS")
54701e916f6782 ("Fixup: perf/x86/intel: Fix NULL event access waring from test robot")
0c9567b36ae6f83c a7138973beb1d124386472663cf 81248d31dd384c71c3b6a6af25a 54701e916f6782039c2ea8adb4b
---------------- --------------------------- --------------------------- ---------------------------
fail:runs %reproduction fail:runs %reproduction fail:runs %reproduction fail:runs
| | | | | | |
:6 100% 6:6 100% 6:6 0% :20 dmesg.WARNING:at_arch/x86/events/intel/ds.c:#intel_pmu_drain_pebs_nhm
>
> diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
> index 65908880f424..3dedf7a0acf6 100644
> --- a/arch/x86/events/intel/ds.c
> +++ b/arch/x86/events/intel/ds.c
> @@ -2781,9 +2781,11 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs
> *iregs, struct perf_sample_d
>
> /* PEBS v3 has more accurate status bits */
> if (x86_pmu.intel_cap.pebs_format >= 3) {
> - for_each_set_bit(bit, (unsigned long *)&pebs_status, size)
> + for_each_set_bit(bit, (unsigned long *)&pebs_status, size) {
> counts[bit]++;
> -
> + if (counts[bit] && !events[bit])
> + events[bit] = cpuc->events[bit];
> + }
> continue;
> }
>
> @@ -2821,8 +2823,11 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs
> *iregs, struct perf_sample_d
> * If collision happened, the record will be dropped.
> */
> if (pebs_status != (1ULL << bit)) {
> - for_each_set_bit(i, (unsigned long *)&pebs_status, size)
> + for_each_set_bit(i, (unsigned long *)&pebs_status, size) {
> error[i]++;
> + if (error[i] && !events[i])
> + events[i] = cpuc->events[i];
> + }
> continue;
> }
>
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [Patch v7 02/12] perf/x86/intel: Fix NULL event access and potential PEBS record loss
2025-10-02 7:09 ` Oliver Sang
@ 2025-10-06 8:03 ` Mi, Dapeng
0 siblings, 0 replies; 22+ messages in thread
From: Mi, Dapeng @ 2025-10-06 8:03 UTC (permalink / raw)
To: Oliver Sang
Cc: oe-lkp, lkp, Kan Liang, linux-perf-users, linux-kernel,
Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Andi Kleen, Eranian Stephane, Dapeng Mi
On 10/2/2025 3:09 PM, Oliver Sang wrote:
> hi, Dapeng,
>
> On Tue, Sep 30, 2025 at 02:19:25PM +0800, Mi, Dapeng wrote:
> [...]
>
>> Oops, it looks previous fix was incomplete. :(
>>
>> Oliver, could you please verify the new attached patch (Please apply this
>> patch on top of the whole patch series)? Thanks a lot for your effort.
> we confirmed the patch fixed the warning we reported.
>
> Tested-by: kernel test robot <oliver.sang@intel.com>
>
> =========================================================================================
> compiler/cpufreq_governor/kconfig/option_a/rootfs/tbox_group/test/testcase:
> gcc-12/performance/x86_64-rhel-9.4/Socket Activity/debian-12-x86_64-phoronix/lkp-csl-2sp7/stress-ng-1.11.0/phoronix-test-suite
>
> commit:
> 0c9567b36ae6f8 ("perf/x86: Remove redundant is_x86_event() prototype")
> a7138973beb1d1 ("perf/x86/intel: Fix NULL event access and potential PEBS record loss")
> 81248d31dd384c ("perf/x86/intel: Add counter group support for arch-PEBS")
> 54701e916f6782 ("Fixup: perf/x86/intel: Fix NULL event access waring from test robot")
>
> 0c9567b36ae6f83c a7138973beb1d124386472663cf 81248d31dd384c71c3b6a6af25a 54701e916f6782039c2ea8adb4b
> ---------------- --------------------------- --------------------------- ---------------------------
> fail:runs %reproduction fail:runs %reproduction fail:runs %reproduction fail:runs
> | | | | | | |
> :6 100% 6:6 100% 6:6 0% :20 dmesg.WARNING:at_arch/x86/events/intel/ds.c:#intel_pmu_drain_pebs_nhm
Oliver, thanks a lot for confirm this. :)
>
>
>> diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
>> index 65908880f424..3dedf7a0acf6 100644
>> --- a/arch/x86/events/intel/ds.c
>> +++ b/arch/x86/events/intel/ds.c
>> @@ -2781,9 +2781,11 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs
>> *iregs, struct perf_sample_d
>>
>> /* PEBS v3 has more accurate status bits */
>> if (x86_pmu.intel_cap.pebs_format >= 3) {
>> - for_each_set_bit(bit, (unsigned long *)&pebs_status, size)
>> + for_each_set_bit(bit, (unsigned long *)&pebs_status, size) {
>> counts[bit]++;
>> -
>> + if (counts[bit] && !events[bit])
>> + events[bit] = cpuc->events[bit];
>> + }
>> continue;
>> }
>>
>> @@ -2821,8 +2823,11 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs
>> *iregs, struct perf_sample_d
>> * If collision happened, the record will be dropped.
>> */
>> if (pebs_status != (1ULL << bit)) {
>> - for_each_set_bit(i, (unsigned long *)&pebs_status, size)
>> + for_each_set_bit(i, (unsigned long *)&pebs_status, size) {
>> error[i]++;
>> + if (error[i] && !events[i])
>> + events[i] = cpuc->events[i];
>> + }
>> continue;
>> }
>>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Patch v7 03/12] perf/x86/intel: Replace x86_pmu.drain_pebs calling with static call
2025-08-28 1:34 [Patch v7 00/12] arch-PEBS enabling for Intel platforms Dapeng Mi
2025-08-28 1:34 ` [Patch v7 01/12] perf/x86: Remove redundant is_x86_event() prototype Dapeng Mi
2025-08-28 1:34 ` [Patch v7 02/12] perf/x86/intel: Fix NULL event access and potential PEBS record loss Dapeng Mi
@ 2025-08-28 1:34 ` Dapeng Mi
2025-08-28 1:34 ` [Patch v7 04/12] perf/x86/intel: Correct large PEBS flag check Dapeng Mi
` (10 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Dapeng Mi @ 2025-08-28 1:34 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Kan Liang, Andi Kleen, Eranian Stephane
Cc: linux-kernel, linux-perf-users, Dapeng Mi, Dapeng Mi
Use x86_pmu_drain_pebs static call to replace calling x86_pmu.drain_pebs
function pointer.
Suggested-by: Peter Zijlstra <peterz@infradead.org>
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/intel/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 28f5468a6ea3..46a000eb0bb3 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3269,7 +3269,7 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status)
* The PEBS buffer has to be drained before handling the A-PMI
*/
if (is_pebs_counter_event_group(event))
- x86_pmu.drain_pebs(regs, &data);
+ static_call(x86_pmu_drain_pebs)(regs, &data);
last_period = event->hw.last_period;
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [Patch v7 04/12] perf/x86/intel: Correct large PEBS flag check
2025-08-28 1:34 [Patch v7 00/12] arch-PEBS enabling for Intel platforms Dapeng Mi
` (2 preceding siblings ...)
2025-08-28 1:34 ` [Patch v7 03/12] perf/x86/intel: Replace x86_pmu.drain_pebs calling with static call Dapeng Mi
@ 2025-08-28 1:34 ` Dapeng Mi
2025-08-28 1:34 ` [Patch v7 05/12] perf/x86/intel: Initialize architectural PEBS Dapeng Mi
` (9 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Dapeng Mi @ 2025-08-28 1:34 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Kan Liang, Andi Kleen, Eranian Stephane
Cc: linux-kernel, linux-perf-users, Dapeng Mi, Dapeng Mi
current large PEBS flag check only checks if sample_regs_user contains
unsupported GPRs but doesn't check if sample_regs_intr contains
unsupported GPRs.
Of course, currently PEBS HW supports to sample all perf supported GPRs,
the missed check doesn't cause real issue. But it won't be true any more
after the subsequent patches support to sample SSP register. SSP
sampling is not supported by adaptive PEBS HW and it would be supported
until arch-PEBS HW. So correct this issue.
Fixes: a47ba4d77e12 ("perf/x86: Enable free running PEBS for REGS_USER/INTR")
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/intel/core.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 46a000eb0bb3..c88bcd5d2bc4 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4029,7 +4029,9 @@ static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
if (!event->attr.exclude_kernel)
flags &= ~PERF_SAMPLE_REGS_USER;
if (event->attr.sample_regs_user & ~PEBS_GP_REGS)
- flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
+ flags &= ~PERF_SAMPLE_REGS_USER;
+ if (event->attr.sample_regs_intr & ~PEBS_GP_REGS)
+ flags &= ~PERF_SAMPLE_REGS_INTR;
return flags;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [Patch v7 05/12] perf/x86/intel: Initialize architectural PEBS
2025-08-28 1:34 [Patch v7 00/12] arch-PEBS enabling for Intel platforms Dapeng Mi
` (3 preceding siblings ...)
2025-08-28 1:34 ` [Patch v7 04/12] perf/x86/intel: Correct large PEBS flag check Dapeng Mi
@ 2025-08-28 1:34 ` Dapeng Mi
2025-08-28 1:34 ` [Patch v7 06/12] perf/x86/intel/ds: Factor out PEBS record processing code to functions Dapeng Mi
` (8 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Dapeng Mi @ 2025-08-28 1:34 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Kan Liang, Andi Kleen, Eranian Stephane
Cc: linux-kernel, linux-perf-users, Dapeng Mi, Dapeng Mi
arch-PEBS leverages CPUID.23H.4/5 sub-leaves enumerate arch-PEBS
supported capabilities and counters bitmap. This patch parses these 2
sub-leaves and initializes arch-PEBS capabilities and corresponding
structures.
Since IA32_PEBS_ENABLE and MSR_PEBS_DATA_CFG MSRs are no longer existed
for arch-PEBS, arch-PEBS doesn't need to manipulate these MSRs. Thus add
a simple pair of __intel_pmu_pebs_enable/disable() callbacks for
arch-PEBS.
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/core.c | 21 +++++++++---
arch/x86/events/intel/core.c | 55 +++++++++++++++++++++++--------
arch/x86/events/intel/ds.c | 52 ++++++++++++++++++++++++-----
arch/x86/events/perf_event.h | 25 ++++++++++++--
arch/x86/include/asm/perf_event.h | 7 +++-
5 files changed, 129 insertions(+), 31 deletions(-)
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 745caa6c15a3..8c25ad2bf179 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -554,14 +554,22 @@ static inline int precise_br_compat(struct perf_event *event)
return m == b;
}
-int x86_pmu_max_precise(void)
+int x86_pmu_max_precise(struct pmu *pmu)
{
int precise = 0;
- /* Support for constant skid */
if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
- precise++;
+ /* arch PEBS */
+ if (x86_pmu.arch_pebs) {
+ precise = 2;
+ if (hybrid(pmu, arch_pebs_cap).pdists)
+ precise++;
+
+ return precise;
+ }
+ /* legacy PEBS - support for constant skid */
+ precise++;
/* Support for IP fixup */
if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
precise++;
@@ -569,13 +577,14 @@ int x86_pmu_max_precise(void)
if (x86_pmu.pebs_prec_dist)
precise++;
}
+
return precise;
}
int x86_pmu_hw_config(struct perf_event *event)
{
if (event->attr.precise_ip) {
- int precise = x86_pmu_max_precise();
+ int precise = x86_pmu_max_precise(event->pmu);
if (event->attr.precise_ip > precise)
return -EOPNOTSUPP;
@@ -2629,7 +2638,9 @@ static ssize_t max_precise_show(struct device *cdev,
struct device_attribute *attr,
char *buf)
{
- return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu_max_precise());
+ struct pmu *pmu = dev_get_drvdata(cdev);
+
+ return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu_max_precise(pmu));
}
static DEVICE_ATTR_RO(max_precise);
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index c88bcd5d2bc4..bfb123ff7c9a 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -5273,34 +5273,58 @@ static inline bool intel_pmu_broken_perf_cap(void)
static void update_pmu_cap(struct pmu *pmu)
{
- unsigned int cntr, fixed_cntr, ecx, edx;
- union cpuid35_eax eax;
- union cpuid35_ebx ebx;
+ unsigned int eax, ebx, ecx, edx;
+ union cpuid35_eax eax_0;
+ union cpuid35_ebx ebx_0;
+ u64 cntrs_mask = 0;
+ u64 pebs_mask = 0;
+ u64 pdists_mask = 0;
- cpuid(ARCH_PERFMON_EXT_LEAF, &eax.full, &ebx.full, &ecx, &edx);
+ cpuid(ARCH_PERFMON_EXT_LEAF, &eax_0.full, &ebx_0.full, &ecx, &edx);
- if (ebx.split.umask2)
+ if (ebx_0.split.umask2)
hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_UMASK2;
- if (ebx.split.eq)
+ if (ebx_0.split.eq)
hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_EQ;
- if (eax.split.cntr_subleaf) {
+ if (eax_0.split.cntr_subleaf) {
cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF,
- &cntr, &fixed_cntr, &ecx, &edx);
- hybrid(pmu, cntr_mask64) = cntr;
- hybrid(pmu, fixed_cntr_mask64) = fixed_cntr;
+ &eax, &ebx, &ecx, &edx);
+ hybrid(pmu, cntr_mask64) = eax;
+ hybrid(pmu, fixed_cntr_mask64) = ebx;
+ cntrs_mask = (u64)ebx << INTEL_PMC_IDX_FIXED | eax;
}
- if (eax.split.acr_subleaf) {
+ if (eax_0.split.acr_subleaf) {
cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_ACR_LEAF,
- &cntr, &fixed_cntr, &ecx, &edx);
+ &eax, &ebx, &ecx, &edx);
/* The mask of the counters which can be reloaded */
- hybrid(pmu, acr_cntr_mask64) = cntr | ((u64)fixed_cntr << INTEL_PMC_IDX_FIXED);
+ hybrid(pmu, acr_cntr_mask64) = eax | ((u64)ebx << INTEL_PMC_IDX_FIXED);
/* The mask of the counters which can cause a reload of reloadable counters */
hybrid(pmu, acr_cause_mask64) = ecx | ((u64)edx << INTEL_PMC_IDX_FIXED);
}
+ /* Bits[5:4] should be set simultaneously if arch-PEBS is supported */
+ if (eax_0.split.pebs_caps_subleaf && eax_0.split.pebs_cnts_subleaf) {
+ cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_PEBS_CAP_LEAF,
+ &eax, &ebx, &ecx, &edx);
+ hybrid(pmu, arch_pebs_cap).caps = (u64)ebx << 32;
+
+ cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_PEBS_COUNTER_LEAF,
+ &eax, &ebx, &ecx, &edx);
+ pebs_mask = ((u64)ecx << INTEL_PMC_IDX_FIXED) | eax;
+ pdists_mask = ((u64)edx << INTEL_PMC_IDX_FIXED) | ebx;
+ hybrid(pmu, arch_pebs_cap).counters = pebs_mask;
+ hybrid(pmu, arch_pebs_cap).pdists = pdists_mask;
+
+ if (WARN_ON((pebs_mask | pdists_mask) & ~cntrs_mask))
+ x86_pmu.arch_pebs = 0;
+ } else {
+ WARN_ON(x86_pmu.arch_pebs == 1);
+ x86_pmu.arch_pebs = 0;
+ }
+
if (!intel_pmu_broken_perf_cap()) {
/* Perf Metric (Bit 15) and PEBS via PT (Bit 16) are hybrid enumeration */
rdmsrq(MSR_IA32_PERF_CAPABILITIES, hybrid(pmu, intel_cap).capabilities);
@@ -6252,7 +6276,7 @@ tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i)
static umode_t
pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i)
{
- return x86_pmu.ds_pebs ? attr->mode : 0;
+ return intel_pmu_has_pebs() ? attr->mode : 0;
}
static umode_t
@@ -7728,6 +7752,9 @@ __init int intel_pmu_init(void)
if (!is_hybrid() && boot_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT))
update_pmu_cap(NULL);
+ if (x86_pmu.arch_pebs)
+ pr_cont("Architectural PEBS, ");
+
intel_pmu_check_counters_mask(&x86_pmu.cntr_mask64,
&x86_pmu.fixed_cntr_mask64,
&x86_pmu.intel_ctrl);
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index b71973e140c2..cd3d2752e32b 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -1531,6 +1531,15 @@ static inline void intel_pmu_drain_large_pebs(struct cpu_hw_events *cpuc)
intel_pmu_drain_pebs_buffer();
}
+static void __intel_pmu_pebs_enable(struct perf_event *event)
+{
+ struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
+ struct hw_perf_event *hwc = &event->hw;
+
+ hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
+ cpuc->pebs_enabled |= 1ULL << hwc->idx;
+}
+
void intel_pmu_pebs_enable(struct perf_event *event)
{
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
@@ -1539,9 +1548,7 @@ void intel_pmu_pebs_enable(struct perf_event *event)
struct debug_store *ds = cpuc->ds;
unsigned int idx = hwc->idx;
- hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
-
- cpuc->pebs_enabled |= 1ULL << hwc->idx;
+ __intel_pmu_pebs_enable(event);
if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) && (x86_pmu.version < 5))
cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
@@ -1603,14 +1610,22 @@ void intel_pmu_pebs_del(struct perf_event *event)
pebs_update_state(needed_cb, cpuc, event, false);
}
-void intel_pmu_pebs_disable(struct perf_event *event)
+static void __intel_pmu_pebs_disable(struct perf_event *event)
{
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
struct hw_perf_event *hwc = &event->hw;
intel_pmu_drain_large_pebs(cpuc);
-
cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
+ hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
+}
+
+void intel_pmu_pebs_disable(struct perf_event *event)
+{
+ struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
+ struct hw_perf_event *hwc = &event->hw;
+
+ __intel_pmu_pebs_disable(event);
if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) &&
(x86_pmu.version < 5))
@@ -1622,8 +1637,6 @@ void intel_pmu_pebs_disable(struct perf_event *event)
if (cpuc->enabled)
wrmsrq(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
-
- hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
}
void intel_pmu_pebs_enable_all(void)
@@ -2690,11 +2703,26 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_d
}
}
+static void __init intel_arch_pebs_init(void)
+{
+ /*
+ * Current hybrid platforms always both support arch-PEBS or not
+ * on all kinds of cores. So directly set x86_pmu.arch_pebs flag
+ * if boot cpu supports arch-PEBS.
+ */
+ x86_pmu.arch_pebs = 1;
+ x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
+ x86_pmu.pebs_capable = ~0ULL;
+
+ x86_pmu.pebs_enable = __intel_pmu_pebs_enable;
+ x86_pmu.pebs_disable = __intel_pmu_pebs_disable;
+}
+
/*
* PEBS probe and setup
*/
-void __init intel_pebs_init(void)
+static void __init intel_ds_pebs_init(void)
{
/*
* No support for 32bit formats
@@ -2809,6 +2837,14 @@ void __init intel_pebs_init(void)
}
}
+void __init intel_pebs_init(void)
+{
+ if (x86_pmu.intel_cap.pebs_format == 0xf)
+ intel_arch_pebs_init();
+ else
+ intel_ds_pebs_init();
+}
+
void perf_restore_debug_store(void)
{
struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 285779c73479..ca5289980b52 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -708,6 +708,12 @@ enum hybrid_pmu_type {
hybrid_big_small_tiny = hybrid_big | hybrid_small_tiny,
};
+struct arch_pebs_cap {
+ u64 caps;
+ u64 counters;
+ u64 pdists;
+};
+
struct x86_hybrid_pmu {
struct pmu pmu;
const char *name;
@@ -752,6 +758,8 @@ struct x86_hybrid_pmu {
mid_ack :1,
enabled_ack :1;
+ struct arch_pebs_cap arch_pebs_cap;
+
u64 pebs_data_source[PERF_PEBS_DATA_SOURCE_MAX];
};
@@ -906,7 +914,7 @@ struct x86_pmu {
union perf_capabilities intel_cap;
/*
- * Intel DebugStore bits
+ * Intel DebugStore and PEBS bits
*/
unsigned int bts :1,
bts_active :1,
@@ -917,7 +925,8 @@ struct x86_pmu {
pebs_no_tlb :1,
pebs_no_isolation :1,
pebs_block :1,
- pebs_ept :1;
+ pebs_ept :1,
+ arch_pebs :1;
int pebs_record_size;
int pebs_buffer_size;
u64 pebs_events_mask;
@@ -929,6 +938,11 @@ struct x86_pmu {
u64 rtm_abort_event;
u64 pebs_capable;
+ /*
+ * Intel Architectural PEBS
+ */
+ struct arch_pebs_cap arch_pebs_cap;
+
/*
* Intel LBR
*/
@@ -1216,7 +1230,7 @@ int x86_reserve_hardware(void);
void x86_release_hardware(void);
-int x86_pmu_max_precise(void);
+int x86_pmu_max_precise(struct pmu *pmu);
void hw_perf_lbr_event_destroy(struct perf_event *event);
@@ -1791,6 +1805,11 @@ static inline int intel_pmu_max_num_pebs(struct pmu *pmu)
return fls((u32)hybrid(pmu, pebs_events_mask));
}
+static inline bool intel_pmu_has_pebs(void)
+{
+ return x86_pmu.ds_pebs || x86_pmu.arch_pebs;
+}
+
#else /* CONFIG_CPU_SUP_INTEL */
static inline void reserve_ds_buffers(void)
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 49a4d442f3fc..0dfa06722bab 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -200,6 +200,8 @@ union cpuid10_edx {
#define ARCH_PERFMON_EXT_LEAF 0x00000023
#define ARCH_PERFMON_NUM_COUNTER_LEAF 0x1
#define ARCH_PERFMON_ACR_LEAF 0x2
+#define ARCH_PERFMON_PEBS_CAP_LEAF 0x4
+#define ARCH_PERFMON_PEBS_COUNTER_LEAF 0x5
union cpuid35_eax {
struct {
@@ -210,7 +212,10 @@ union cpuid35_eax {
unsigned int acr_subleaf:1;
/* Events Sub-Leaf */
unsigned int events_subleaf:1;
- unsigned int reserved:28;
+ /* arch-PEBS Sub-Leaves */
+ unsigned int pebs_caps_subleaf:1;
+ unsigned int pebs_cnts_subleaf:1;
+ unsigned int reserved:26;
} split;
unsigned int full;
};
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [Patch v7 06/12] perf/x86/intel/ds: Factor out PEBS record processing code to functions
2025-08-28 1:34 [Patch v7 00/12] arch-PEBS enabling for Intel platforms Dapeng Mi
` (4 preceding siblings ...)
2025-08-28 1:34 ` [Patch v7 05/12] perf/x86/intel: Initialize architectural PEBS Dapeng Mi
@ 2025-08-28 1:34 ` Dapeng Mi
2025-08-28 1:34 ` [Patch v7 07/12] perf/x86/intel/ds: Factor out PEBS group " Dapeng Mi
` (7 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Dapeng Mi @ 2025-08-28 1:34 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Kan Liang, Andi Kleen, Eranian Stephane
Cc: linux-kernel, linux-perf-users, Dapeng Mi, Dapeng Mi
Beside some PEBS record layout difference, arch-PEBS can share most of
PEBS record processing code with adaptive PEBS. Thus, factor out these
common processing code to independent inline functions, so they can be
reused by subsequent arch-PEBS handler.
Suggested-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/intel/ds.c | 101 ++++++++++++++++++++++++-------------
1 file changed, 66 insertions(+), 35 deletions(-)
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index cd3d2752e32b..7a100467d635 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -2624,6 +2624,64 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_d
}
}
+static inline void __intel_pmu_handle_pebs_record(struct pt_regs *iregs,
+ struct pt_regs *regs,
+ struct perf_sample_data *data,
+ void *at, u64 pebs_status,
+ struct perf_event *events[],
+ short *counts, void **last,
+ setup_fn setup_sample)
+{
+ struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
+ struct perf_event *event;
+ int bit;
+
+ for_each_set_bit(bit, (unsigned long *)&pebs_status, X86_PMC_IDX_MAX) {
+ event = cpuc->events[bit];
+
+ if (WARN_ON_ONCE(!event) ||
+ WARN_ON_ONCE(!event->attr.precise_ip))
+ continue;
+
+ if (counts[bit]++)
+ __intel_pmu_pebs_event(event, iregs, regs, data,
+ last[bit], setup_sample);
+
+ last[bit] = at;
+ /*
+ * perf_event_overflow() called by below __intel_pmu_pebs_last_event()
+ * could trigger interrupt throttle and clear all event pointers of
+ * the group in cpuc->events[] to NULL. So snapshot the event[] before
+ * it could be cleared. This avoids the possible NULL event pointer
+ * access and PEBS record loss.
+ */
+ if (counts[bit] && !events[bit])
+ events[bit] = cpuc->events[bit];
+ }
+}
+
+static inline void
+__intel_pmu_handle_last_pebs_record(struct pt_regs *iregs, struct pt_regs *regs,
+ struct perf_sample_data *data, u64 mask,
+ struct perf_event *events[],
+ short *counts, void **last,
+ setup_fn setup_sample)
+{
+ struct perf_event *event;
+ int bit;
+
+ for_each_set_bit(bit, (unsigned long *)&mask, X86_PMC_IDX_MAX) {
+ if (!counts[bit])
+ continue;
+
+ event = events[bit];
+
+ __intel_pmu_pebs_last_event(event, iregs, regs, data, last[bit],
+ counts[bit], setup_sample);
+ }
+
+}
+
static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_data *data)
{
struct perf_event *events[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {NULL};
@@ -2634,9 +2692,7 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_d
struct x86_perf_regs perf_regs;
struct pt_regs *regs = &perf_regs.regs;
struct pebs_basic *basic;
- struct perf_event *event;
void *base, *at, *top;
- int bit;
u64 mask;
if (!x86_pmu.pebs_active)
@@ -2649,6 +2705,7 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_d
mask = hybrid(cpuc->pmu, pebs_events_mask) |
(hybrid(cpuc->pmu, fixed_cntr_mask64) << INTEL_PMC_IDX_FIXED);
+ mask &= cpuc->pebs_enabled;
if (unlikely(base >= top)) {
intel_pmu_pebs_event_update_no_drain(cpuc, mask);
@@ -2666,41 +2723,15 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_d
if (basic->format_size != cpuc->pebs_record_size)
continue;
- pebs_status = basic->applicable_counters & cpuc->pebs_enabled & mask;
- for_each_set_bit(bit, (unsigned long *)&pebs_status, X86_PMC_IDX_MAX) {
- event = cpuc->events[bit];
-
- if (WARN_ON_ONCE(!event) ||
- WARN_ON_ONCE(!event->attr.precise_ip))
- continue;
-
- if (counts[bit]++) {
- __intel_pmu_pebs_event(event, iregs, regs, data, last[bit],
- setup_pebs_adaptive_sample_data);
- }
- last[bit] = at;
-
- /*
- * perf_event_overflow() called by below __intel_pmu_pebs_last_event()
- * could trigger interrupt throttle and clear all event pointers of
- * the group in cpuc->events[] to NULL. So snapshot the event[] before
- * it could be cleared. This avoids the possible NULL event pointer
- * access and PEBS record loss.
- */
- if (counts[bit] && !events[bit])
- events[bit] = cpuc->events[bit];
- }
+ pebs_status = mask & basic->applicable_counters;
+ __intel_pmu_handle_pebs_record(iregs, regs, data, at,
+ pebs_status, events, counts, last,
+ setup_pebs_adaptive_sample_data);
}
- for_each_set_bit(bit, (unsigned long *)&mask, X86_PMC_IDX_MAX) {
- if (!counts[bit])
- continue;
-
- event = events[bit];
-
- __intel_pmu_pebs_last_event(event, iregs, regs, data, last[bit],
- counts[bit], setup_pebs_adaptive_sample_data);
- }
+ __intel_pmu_handle_last_pebs_record(iregs, regs, data, mask, events,
+ counts, last,
+ setup_pebs_adaptive_sample_data);
}
static void __init intel_arch_pebs_init(void)
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [Patch v7 07/12] perf/x86/intel/ds: Factor out PEBS group processing code to functions
2025-08-28 1:34 [Patch v7 00/12] arch-PEBS enabling for Intel platforms Dapeng Mi
` (5 preceding siblings ...)
2025-08-28 1:34 ` [Patch v7 06/12] perf/x86/intel/ds: Factor out PEBS record processing code to functions Dapeng Mi
@ 2025-08-28 1:34 ` Dapeng Mi
2025-08-28 1:34 ` [Patch v7 08/12] perf/x86/intel: Process arch-PEBS records or record fragments Dapeng Mi
` (6 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Dapeng Mi @ 2025-08-28 1:34 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Kan Liang, Andi Kleen, Eranian Stephane
Cc: linux-kernel, linux-perf-users, Dapeng Mi, Dapeng Mi
Adaptive PEBS and arch-PEBS share lots of same code to process these
PEBS groups, like basic, GPR and meminfo groups. Extract these shared
code to generic functions to avoid duplicated code.
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/intel/ds.c | 170 +++++++++++++++++++++++--------------
1 file changed, 104 insertions(+), 66 deletions(-)
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 7a100467d635..121042d532b8 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -2072,6 +2072,90 @@ static inline void __setup_pebs_counter_group(struct cpu_hw_events *cpuc,
#define PEBS_LATENCY_MASK 0xffff
+static inline void __setup_perf_sample_data(struct perf_event *event,
+ struct pt_regs *iregs,
+ struct perf_sample_data *data)
+{
+ perf_sample_data_init(data, 0, event->hw.last_period);
+
+ /*
+ * We must however always use iregs for the unwinder to stay sane; the
+ * record BP,SP,IP can point into thin air when the record is from a
+ * previous PMI context or an (I)RET happened between the record and
+ * PMI.
+ */
+ perf_sample_save_callchain(data, event, iregs);
+}
+
+static inline void __setup_pebs_basic_group(struct perf_event *event,
+ struct pt_regs *regs,
+ struct perf_sample_data *data,
+ u64 sample_type, u64 ip,
+ u64 tsc, u16 retire)
+{
+ /* The ip in basic is EventingIP */
+ set_linear_ip(regs, ip);
+ regs->flags = PERF_EFLAGS_EXACT;
+ setup_pebs_time(event, data, tsc);
+
+ if (sample_type & PERF_SAMPLE_WEIGHT_STRUCT)
+ data->weight.var3_w = retire;
+}
+
+static inline void __setup_pebs_gpr_group(struct perf_event *event,
+ struct pt_regs *regs,
+ struct pebs_gprs *gprs,
+ u64 sample_type)
+{
+ if (event->attr.precise_ip < 2) {
+ set_linear_ip(regs, gprs->ip);
+ regs->flags &= ~PERF_EFLAGS_EXACT;
+ }
+
+ if (sample_type & (PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER))
+ adaptive_pebs_save_regs(regs, gprs);
+}
+
+static inline void __setup_pebs_meminfo_group(struct perf_event *event,
+ struct perf_sample_data *data,
+ u64 sample_type, u64 latency,
+ u16 instr_latency, u64 address,
+ u64 aux, u64 tsx_tuning, u64 ax)
+{
+ if (sample_type & PERF_SAMPLE_WEIGHT_TYPE) {
+ u64 tsx_latency = intel_get_tsx_weight(tsx_tuning);
+
+ data->weight.var2_w = instr_latency;
+
+ /*
+ * Although meminfo::latency is defined as a u64,
+ * only the lower 32 bits include the valid data
+ * in practice on Ice Lake and earlier platforms.
+ */
+ if (sample_type & PERF_SAMPLE_WEIGHT)
+ data->weight.full = latency ?: tsx_latency;
+ else
+ data->weight.var1_dw = (u32)latency ?: tsx_latency;
+
+ data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE;
+ }
+
+ if (sample_type & PERF_SAMPLE_DATA_SRC) {
+ data->data_src.val = get_data_src(event, aux);
+ data->sample_flags |= PERF_SAMPLE_DATA_SRC;
+ }
+
+ if (sample_type & PERF_SAMPLE_ADDR_TYPE) {
+ data->addr = address;
+ data->sample_flags |= PERF_SAMPLE_ADDR;
+ }
+
+ if (sample_type & PERF_SAMPLE_TRANSACTION) {
+ data->txn = intel_get_tsx_transaction(tsx_tuning, ax);
+ data->sample_flags |= PERF_SAMPLE_TRANSACTION;
+ }
+}
+
/*
* With adaptive PEBS the layout depends on what fields are configured.
*/
@@ -2081,12 +2165,14 @@ static void setup_pebs_adaptive_sample_data(struct perf_event *event,
struct pt_regs *regs)
{
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
+ u64 sample_type = event->attr.sample_type;
struct pebs_basic *basic = __pebs;
void *next_record = basic + 1;
- u64 sample_type, format_group;
struct pebs_meminfo *meminfo = NULL;
struct pebs_gprs *gprs = NULL;
struct x86_perf_regs *perf_regs;
+ u64 format_group;
+ u16 retire;
if (basic == NULL)
return;
@@ -2094,31 +2180,17 @@ static void setup_pebs_adaptive_sample_data(struct perf_event *event,
perf_regs = container_of(regs, struct x86_perf_regs, regs);
perf_regs->xmm_regs = NULL;
- sample_type = event->attr.sample_type;
format_group = basic->format_group;
- perf_sample_data_init(data, 0, event->hw.last_period);
- setup_pebs_time(event, data, basic->tsc);
-
- /*
- * We must however always use iregs for the unwinder to stay sane; the
- * record BP,SP,IP can point into thin air when the record is from a
- * previous PMI context or an (I)RET happened between the record and
- * PMI.
- */
- perf_sample_save_callchain(data, event, iregs);
+ __setup_perf_sample_data(event, iregs, data);
*regs = *iregs;
- /* The ip in basic is EventingIP */
- set_linear_ip(regs, basic->ip);
- regs->flags = PERF_EFLAGS_EXACT;
- if (sample_type & PERF_SAMPLE_WEIGHT_STRUCT) {
- if (x86_pmu.flags & PMU_FL_RETIRE_LATENCY)
- data->weight.var3_w = basic->retire_latency;
- else
- data->weight.var3_w = 0;
- }
+ /* basic group */
+ retire = x86_pmu.flags & PMU_FL_RETIRE_LATENCY ?
+ basic->retire_latency : 0;
+ __setup_pebs_basic_group(event, regs, data, sample_type,
+ basic->ip, basic->tsc, retire);
/*
* The record for MEMINFO is in front of GP
@@ -2134,54 +2206,20 @@ static void setup_pebs_adaptive_sample_data(struct perf_event *event,
gprs = next_record;
next_record = gprs + 1;
- if (event->attr.precise_ip < 2) {
- set_linear_ip(regs, gprs->ip);
- regs->flags &= ~PERF_EFLAGS_EXACT;
- }
-
- if (sample_type & (PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER))
- adaptive_pebs_save_regs(regs, gprs);
+ __setup_pebs_gpr_group(event, regs, gprs, sample_type);
}
if (format_group & PEBS_DATACFG_MEMINFO) {
- if (sample_type & PERF_SAMPLE_WEIGHT_TYPE) {
- u64 latency = x86_pmu.flags & PMU_FL_INSTR_LATENCY ?
- meminfo->cache_latency : meminfo->mem_latency;
-
- if (x86_pmu.flags & PMU_FL_INSTR_LATENCY)
- data->weight.var2_w = meminfo->instr_latency;
-
- /*
- * Although meminfo::latency is defined as a u64,
- * only the lower 32 bits include the valid data
- * in practice on Ice Lake and earlier platforms.
- */
- if (sample_type & PERF_SAMPLE_WEIGHT) {
- data->weight.full = latency ?:
- intel_get_tsx_weight(meminfo->tsx_tuning);
- } else {
- data->weight.var1_dw = (u32)latency ?:
- intel_get_tsx_weight(meminfo->tsx_tuning);
- }
-
- data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE;
- }
-
- if (sample_type & PERF_SAMPLE_DATA_SRC) {
- data->data_src.val = get_data_src(event, meminfo->aux);
- data->sample_flags |= PERF_SAMPLE_DATA_SRC;
- }
-
- if (sample_type & PERF_SAMPLE_ADDR_TYPE) {
- data->addr = meminfo->address;
- data->sample_flags |= PERF_SAMPLE_ADDR;
- }
-
- if (sample_type & PERF_SAMPLE_TRANSACTION) {
- data->txn = intel_get_tsx_transaction(meminfo->tsx_tuning,
- gprs ? gprs->ax : 0);
- data->sample_flags |= PERF_SAMPLE_TRANSACTION;
- }
+ u64 latency = x86_pmu.flags & PMU_FL_INSTR_LATENCY ?
+ meminfo->cache_latency : meminfo->mem_latency;
+ u64 instr_latency = x86_pmu.flags & PMU_FL_INSTR_LATENCY ?
+ meminfo->instr_latency : 0;
+ u64 ax = gprs ? gprs->ax : 0;
+
+ __setup_pebs_meminfo_group(event, data, sample_type, latency,
+ instr_latency, meminfo->address,
+ meminfo->aux, meminfo->tsx_tuning,
+ ax);
}
if (format_group & PEBS_DATACFG_XMMS) {
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [Patch v7 08/12] perf/x86/intel: Process arch-PEBS records or record fragments
2025-08-28 1:34 [Patch v7 00/12] arch-PEBS enabling for Intel platforms Dapeng Mi
` (6 preceding siblings ...)
2025-08-28 1:34 ` [Patch v7 07/12] perf/x86/intel/ds: Factor out PEBS group " Dapeng Mi
@ 2025-08-28 1:34 ` Dapeng Mi
2025-08-28 1:34 ` [Patch v7 09/12] perf/x86/intel: Allocate arch-PEBS buffer and initialize PEBS_BASE MSR Dapeng Mi
` (5 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Dapeng Mi @ 2025-08-28 1:34 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Kan Liang, Andi Kleen, Eranian Stephane
Cc: linux-kernel, linux-perf-users, Dapeng Mi, Dapeng Mi
A significant difference with adaptive PEBS is that arch-PEBS record
supports fragments which means an arch-PEBS record could be split into
several independent fragments which have its own arch-PEBS header in
each fragment.
This patch defines architectural PEBS record layout structures and add
helpers to process arch-PEBS records or fragments. Only legacy PEBS
groups like basic, GPR, XMM and LBR groups are supported in this patch,
the new added YMM/ZMM/OPMASK vector registers capturing would be
supported in the future.
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/intel/core.c | 13 +++
arch/x86/events/intel/ds.c | 182 ++++++++++++++++++++++++++++++
arch/x86/include/asm/msr-index.h | 6 +
arch/x86/include/asm/perf_event.h | 96 ++++++++++++++++
4 files changed, 297 insertions(+)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index bfb123ff7c9a..cab2ce73ad09 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3215,6 +3215,19 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status)
status &= ~GLOBAL_STATUS_PERF_METRICS_OVF_BIT;
}
+ /*
+ * Arch PEBS sets bit 54 in the global status register
+ */
+ if (__test_and_clear_bit(GLOBAL_STATUS_ARCH_PEBS_THRESHOLD_BIT,
+ (unsigned long *)&status)) {
+ handled++;
+ static_call(x86_pmu_drain_pebs)(regs, &data);
+
+ if (cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS] &&
+ is_pebs_counter_event_group(cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS]))
+ status &= ~GLOBAL_STATUS_PERF_METRICS_OVF_BIT;
+ }
+
/*
* Intel PT
*/
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 121042d532b8..311e25d5c4cf 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -2270,6 +2270,114 @@ static void setup_pebs_adaptive_sample_data(struct perf_event *event,
format_group);
}
+static inline bool arch_pebs_record_continued(struct arch_pebs_header *header)
+{
+ /* Continue bit or null PEBS record indicates fragment follows. */
+ return header->cont || !(header->format & GENMASK_ULL(63, 16));
+}
+
+static void setup_arch_pebs_sample_data(struct perf_event *event,
+ struct pt_regs *iregs, void *__pebs,
+ struct perf_sample_data *data,
+ struct pt_regs *regs)
+{
+ struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
+ u64 sample_type = event->attr.sample_type;
+ struct arch_pebs_header *header = NULL;
+ struct arch_pebs_aux *meminfo = NULL;
+ struct arch_pebs_gprs *gprs = NULL;
+ struct x86_perf_regs *perf_regs;
+ void *next_record;
+ void *at = __pebs;
+
+ if (at == NULL)
+ return;
+
+ perf_regs = container_of(regs, struct x86_perf_regs, regs);
+ perf_regs->xmm_regs = NULL;
+
+ __setup_perf_sample_data(event, iregs, data);
+
+ *regs = *iregs;
+
+again:
+ header = at;
+ next_record = at + sizeof(struct arch_pebs_header);
+ if (header->basic) {
+ struct arch_pebs_basic *basic = next_record;
+ u16 retire = 0;
+
+ next_record = basic + 1;
+
+ if (sample_type & PERF_SAMPLE_WEIGHT_STRUCT)
+ retire = basic->valid ? basic->retire : 0;
+ __setup_pebs_basic_group(event, regs, data, sample_type,
+ basic->ip, basic->tsc, retire);
+ }
+
+ /*
+ * The record for MEMINFO is in front of GP
+ * But PERF_SAMPLE_TRANSACTION needs gprs->ax.
+ * Save the pointer here but process later.
+ */
+ if (header->aux) {
+ meminfo = next_record;
+ next_record = meminfo + 1;
+ }
+
+ if (header->gpr) {
+ gprs = next_record;
+ next_record = gprs + 1;
+
+ __setup_pebs_gpr_group(event, regs, (struct pebs_gprs *)gprs,
+ sample_type);
+ }
+
+ if (header->aux) {
+ u64 ax = gprs ? gprs->ax : 0;
+
+ __setup_pebs_meminfo_group(event, data, sample_type,
+ meminfo->cache_latency,
+ meminfo->instr_latency,
+ meminfo->address, meminfo->aux,
+ meminfo->tsx_tuning, ax);
+ }
+
+ if (header->xmm) {
+ struct pebs_xmm *xmm;
+
+ next_record += sizeof(struct arch_pebs_xer_header);
+
+ xmm = next_record;
+ perf_regs->xmm_regs = xmm->xmm;
+ next_record = xmm + 1;
+ }
+
+ if (header->lbr) {
+ struct arch_pebs_lbr_header *lbr_header = next_record;
+ struct lbr_entry *lbr;
+ int num_lbr;
+
+ next_record = lbr_header + 1;
+ lbr = next_record;
+
+ num_lbr = header->lbr == ARCH_PEBS_LBR_NUM_VAR ? lbr_header->depth :
+ header->lbr * ARCH_PEBS_BASE_LBR_ENTRIES;
+ next_record += num_lbr * sizeof(struct lbr_entry);
+
+ if (has_branch_stack(event)) {
+ intel_pmu_store_pebs_lbrs(lbr);
+ intel_pmu_lbr_save_brstack(data, cpuc, event);
+ }
+ }
+
+ /* Parse followed fragments if there are. */
+ if (arch_pebs_record_continued(header)) {
+ at = at + header->size;
+ goto again;
+ }
+}
+
static inline void *
get_next_pebs_record_by_bit(void *base, void *top, int bit)
{
@@ -2772,6 +2880,79 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_d
setup_pebs_adaptive_sample_data);
}
+static void intel_pmu_drain_arch_pebs(struct pt_regs *iregs,
+ struct perf_sample_data *data)
+{
+ struct perf_event *events[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {NULL};
+ short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
+ void *last[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS];
+ struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
+ union arch_pebs_index index;
+ struct x86_perf_regs perf_regs;
+ struct pt_regs *regs = &perf_regs.regs;
+ void *base, *at, *top;
+ u64 mask;
+
+ rdmsrq(MSR_IA32_PEBS_INDEX, index.whole);
+
+ if (unlikely(!index.wr)) {
+ intel_pmu_pebs_event_update_no_drain(cpuc, X86_PMC_IDX_MAX);
+ return;
+ }
+
+ base = cpuc->ds_pebs_vaddr;
+ top = (void *)((u64)cpuc->ds_pebs_vaddr +
+ (index.wr << ARCH_PEBS_INDEX_WR_SHIFT));
+
+ index.wr = 0;
+ index.full = 0;
+ wrmsrq(MSR_IA32_PEBS_INDEX, index.whole);
+
+ mask = hybrid(cpuc->pmu, arch_pebs_cap).counters & cpuc->pebs_enabled;
+
+ if (!iregs)
+ iregs = &dummy_iregs;
+
+ /* Process all but the last event for each counter. */
+ for (at = base; at < top;) {
+ struct arch_pebs_header *header;
+ struct arch_pebs_basic *basic;
+ u64 pebs_status;
+
+ header = at;
+
+ if (WARN_ON_ONCE(!header->size))
+ break;
+
+ /* 1st fragment or single record must have basic group */
+ if (!header->basic) {
+ at += header->size;
+ continue;
+ }
+
+ basic = at + sizeof(struct arch_pebs_header);
+ pebs_status = mask & basic->applicable_counters;
+ __intel_pmu_handle_pebs_record(iregs, regs, data, at,
+ pebs_status, events, counts, last,
+ setup_arch_pebs_sample_data);
+
+ /* Skip non-last fragments */
+ while (arch_pebs_record_continued(header)) {
+ if (!header->size)
+ break;
+ at += header->size;
+ header = at;
+ }
+
+ /* Skip last fragment or the single record */
+ at += header->size;
+ }
+
+ __intel_pmu_handle_last_pebs_record(iregs, regs, data, mask, events,
+ counts, last,
+ setup_arch_pebs_sample_data);
+}
+
static void __init intel_arch_pebs_init(void)
{
/*
@@ -2781,6 +2962,7 @@ static void __init intel_arch_pebs_init(void)
*/
x86_pmu.arch_pebs = 1;
x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
+ x86_pmu.drain_pebs = intel_pmu_drain_arch_pebs;
x86_pmu.pebs_capable = ~0ULL;
x86_pmu.pebs_enable = __intel_pmu_pebs_enable;
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index f627196eb796..7c306dd0713c 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -324,6 +324,12 @@
PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE | \
PERF_CAP_PEBS_TIMING_INFO)
+/* Arch PEBS */
+#define MSR_IA32_PEBS_BASE 0x000003f4
+#define MSR_IA32_PEBS_INDEX 0x000003f5
+#define ARCH_PEBS_OFFSET_MASK 0x7fffff
+#define ARCH_PEBS_INDEX_WR_SHIFT 4
+
#define MSR_IA32_RTIT_CTL 0x00000570
#define RTIT_CTL_TRACEEN BIT(0)
#define RTIT_CTL_CYCLEACC BIT(1)
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 0dfa06722bab..3b3848f0d339 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -437,6 +437,8 @@ static inline bool is_topdown_idx(int idx)
#define GLOBAL_STATUS_LBRS_FROZEN BIT_ULL(GLOBAL_STATUS_LBRS_FROZEN_BIT)
#define GLOBAL_STATUS_TRACE_TOPAPMI_BIT 55
#define GLOBAL_STATUS_TRACE_TOPAPMI BIT_ULL(GLOBAL_STATUS_TRACE_TOPAPMI_BIT)
+#define GLOBAL_STATUS_ARCH_PEBS_THRESHOLD_BIT 54
+#define GLOBAL_STATUS_ARCH_PEBS_THRESHOLD BIT_ULL(GLOBAL_STATUS_ARCH_PEBS_THRESHOLD_BIT)
#define GLOBAL_STATUS_PERF_METRICS_OVF_BIT 48
#define GLOBAL_CTRL_EN_PERF_METRICS BIT_ULL(48)
@@ -507,6 +509,100 @@ struct pebs_cntr_header {
#define INTEL_CNTR_METRICS 0x3
+/*
+ * Arch PEBS
+ */
+union arch_pebs_index {
+ struct {
+ u64 rsvd:4,
+ wr:23,
+ rsvd2:4,
+ full:1,
+ en:1,
+ rsvd3:3,
+ thresh:23,
+ rsvd4:5;
+ };
+ u64 whole;
+};
+
+struct arch_pebs_header {
+ union {
+ u64 format;
+ struct {
+ u64 size:16, /* Record size */
+ rsvd:14,
+ mode:1, /* 64BIT_MODE */
+ cont:1,
+ rsvd2:3,
+ cntr:5,
+ lbr:2,
+ rsvd3:7,
+ xmm:1,
+ ymmh:1,
+ rsvd4:2,
+ opmask:1,
+ zmmh:1,
+ h16zmm:1,
+ rsvd5:5,
+ gpr:1,
+ aux:1,
+ basic:1;
+ };
+ };
+ u64 rsvd6;
+};
+
+struct arch_pebs_basic {
+ u64 ip;
+ u64 applicable_counters;
+ u64 tsc;
+ u64 retire :16, /* Retire Latency */
+ valid :1,
+ rsvd :47;
+ u64 rsvd2;
+ u64 rsvd3;
+};
+
+struct arch_pebs_aux {
+ u64 address;
+ u64 rsvd;
+ u64 rsvd2;
+ u64 rsvd3;
+ u64 rsvd4;
+ u64 aux;
+ u64 instr_latency :16,
+ pad2 :16,
+ cache_latency :16,
+ pad3 :16;
+ u64 tsx_tuning;
+};
+
+struct arch_pebs_gprs {
+ u64 flags, ip, ax, cx, dx, bx, sp, bp, si, di;
+ u64 r8, r9, r10, r11, r12, r13, r14, r15, ssp;
+ u64 rsvd;
+};
+
+struct arch_pebs_xer_header {
+ u64 xstate;
+ u64 rsvd;
+};
+
+#define ARCH_PEBS_LBR_NAN 0x0
+#define ARCH_PEBS_LBR_NUM_8 0x1
+#define ARCH_PEBS_LBR_NUM_16 0x2
+#define ARCH_PEBS_LBR_NUM_VAR 0x3
+#define ARCH_PEBS_BASE_LBR_ENTRIES 8
+struct arch_pebs_lbr_header {
+ u64 rsvd;
+ u64 ctl;
+ u64 depth;
+ u64 ler_from;
+ u64 ler_to;
+ u64 ler_info;
+};
+
/*
* AMD Extended Performance Monitoring and Debug cpuid feature detection
*/
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [Patch v7 09/12] perf/x86/intel: Allocate arch-PEBS buffer and initialize PEBS_BASE MSR
2025-08-28 1:34 [Patch v7 00/12] arch-PEBS enabling for Intel platforms Dapeng Mi
` (7 preceding siblings ...)
2025-08-28 1:34 ` [Patch v7 08/12] perf/x86/intel: Process arch-PEBS records or record fragments Dapeng Mi
@ 2025-08-28 1:34 ` Dapeng Mi
2025-08-28 1:34 ` [Patch v7 10/12] perf/x86/intel: Update dyn_constranit base on PEBS event precise level Dapeng Mi
` (4 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Dapeng Mi @ 2025-08-28 1:34 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Kan Liang, Andi Kleen, Eranian Stephane
Cc: linux-kernel, linux-perf-users, Dapeng Mi, Dapeng Mi
Arch-PEBS introduces a new MSR IA32_PEBS_BASE to store the arch-PEBS
buffer physical address. This patch allocates arch-PEBS buffer and then
initialize IA32_PEBS_BASE MSR with the buffer physical address.
Co-developed-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/intel/core.c | 11 ++++-
arch/x86/events/intel/ds.c | 82 ++++++++++++++++++++++++++++-----
arch/x86/events/perf_event.h | 11 ++++-
arch/x86/include/asm/intel_ds.h | 3 +-
4 files changed, 92 insertions(+), 15 deletions(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index cab2ce73ad09..41c4af6bd62c 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -5227,7 +5227,13 @@ int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
static int intel_pmu_cpu_prepare(int cpu)
{
- return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu);
+ int ret;
+
+ ret = intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu);
+ if (ret)
+ return ret;
+
+ return alloc_arch_pebs_buf_on_cpu(cpu);
}
static void flip_smm_bit(void *data)
@@ -5457,6 +5463,7 @@ static void intel_pmu_cpu_starting(int cpu)
return;
init_debug_store_on_cpu(cpu);
+ init_arch_pebs_on_cpu(cpu);
/*
* Deal with CPUs that don't clear their LBRs on power-up, and that may
* even boot with LBRs enabled.
@@ -5554,6 +5561,7 @@ static void free_excl_cntrs(struct cpu_hw_events *cpuc)
static void intel_pmu_cpu_dying(int cpu)
{
fini_debug_store_on_cpu(cpu);
+ fini_arch_pebs_on_cpu(cpu);
}
void intel_cpuc_finish(struct cpu_hw_events *cpuc)
@@ -5574,6 +5582,7 @@ static void intel_pmu_cpu_dead(int cpu)
{
struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
+ release_arch_pebs_buf_on_cpu(cpu);
intel_cpuc_finish(cpuc);
if (is_hybrid() && cpuc->pmu)
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 311e25d5c4cf..ed9bce51182d 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -625,13 +625,18 @@ static int alloc_pebs_buffer(int cpu)
int max, node = cpu_to_node(cpu);
void *buffer, *insn_buff, *cea;
- if (!x86_pmu.ds_pebs)
+ if (!intel_pmu_has_pebs())
return 0;
buffer = dsalloc_pages(bsiz, GFP_KERNEL, cpu);
if (unlikely(!buffer))
return -ENOMEM;
+ if (x86_pmu.arch_pebs) {
+ hwev->pebs_vaddr = buffer;
+ return 0;
+ }
+
/*
* HSW+ already provides us the eventing ip; no need to allocate this
* buffer then.
@@ -644,7 +649,7 @@ static int alloc_pebs_buffer(int cpu)
}
per_cpu(insn_buffer, cpu) = insn_buff;
}
- hwev->ds_pebs_vaddr = buffer;
+ hwev->pebs_vaddr = buffer;
/* Update the cpu entry area mapping */
cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer;
ds->pebs_buffer_base = (unsigned long) cea;
@@ -660,17 +665,20 @@ static void release_pebs_buffer(int cpu)
struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
void *cea;
- if (!x86_pmu.ds_pebs)
+ if (!intel_pmu_has_pebs())
return;
- kfree(per_cpu(insn_buffer, cpu));
- per_cpu(insn_buffer, cpu) = NULL;
+ if (x86_pmu.ds_pebs) {
+ kfree(per_cpu(insn_buffer, cpu));
+ per_cpu(insn_buffer, cpu) = NULL;
- /* Clear the fixmap */
- cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer;
- ds_clear_cea(cea, x86_pmu.pebs_buffer_size);
- dsfree_pages(hwev->ds_pebs_vaddr, x86_pmu.pebs_buffer_size);
- hwev->ds_pebs_vaddr = NULL;
+ /* Clear the fixmap */
+ cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer;
+ ds_clear_cea(cea, x86_pmu.pebs_buffer_size);
+ }
+
+ dsfree_pages(hwev->pebs_vaddr, x86_pmu.pebs_buffer_size);
+ hwev->pebs_vaddr = NULL;
}
static int alloc_bts_buffer(int cpu)
@@ -823,6 +831,56 @@ void reserve_ds_buffers(void)
}
}
+inline int alloc_arch_pebs_buf_on_cpu(int cpu)
+{
+ if (!x86_pmu.arch_pebs)
+ return 0;
+
+ return alloc_pebs_buffer(cpu);
+}
+
+inline void release_arch_pebs_buf_on_cpu(int cpu)
+{
+ if (!x86_pmu.arch_pebs)
+ return;
+
+ release_pebs_buffer(cpu);
+}
+
+void init_arch_pebs_on_cpu(int cpu)
+{
+ struct cpu_hw_events *cpuc = per_cpu_ptr(&cpu_hw_events, cpu);
+ u64 arch_pebs_base;
+
+ if (!x86_pmu.arch_pebs)
+ return;
+
+ if (!cpuc->pebs_vaddr) {
+ WARN(1, "Fail to allocate PEBS buffer on CPU %d\n", cpu);
+ x86_pmu.pebs_active = 0;
+ return;
+ }
+
+ /*
+ * 4KB-aligned pointer of the output buffer
+ * (__alloc_pages_node() return page aligned address)
+ * Buffer Size = 4KB * 2^SIZE
+ * contiguous physical buffer (__alloc_pages_node() with order)
+ */
+ arch_pebs_base = virt_to_phys(cpuc->pebs_vaddr) | PEBS_BUFFER_SHIFT;
+ wrmsr_on_cpu(cpu, MSR_IA32_PEBS_BASE, (u32)arch_pebs_base,
+ (u32)(arch_pebs_base >> 32));
+ x86_pmu.pebs_active = 1;
+}
+
+inline void fini_arch_pebs_on_cpu(int cpu)
+{
+ if (!x86_pmu.arch_pebs)
+ return;
+
+ wrmsr_on_cpu(cpu, MSR_IA32_PEBS_BASE, 0, 0);
+}
+
/*
* BTS
*/
@@ -2900,8 +2958,8 @@ static void intel_pmu_drain_arch_pebs(struct pt_regs *iregs,
return;
}
- base = cpuc->ds_pebs_vaddr;
- top = (void *)((u64)cpuc->ds_pebs_vaddr +
+ base = cpuc->pebs_vaddr;
+ top = (void *)((u64)cpuc->pebs_vaddr +
(index.wr << ARCH_PEBS_INDEX_WR_SHIFT));
index.wr = 0;
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index ca5289980b52..13f411bca6bc 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -283,8 +283,9 @@ struct cpu_hw_events {
* Intel DebugStore bits
*/
struct debug_store *ds;
- void *ds_pebs_vaddr;
void *ds_bts_vaddr;
+ /* DS based PEBS or arch-PEBS buffer address */
+ void *pebs_vaddr;
u64 pebs_enabled;
int n_pebs;
int n_large_pebs;
@@ -1617,6 +1618,14 @@ extern void intel_cpuc_finish(struct cpu_hw_events *cpuc);
int intel_pmu_init(void);
+int alloc_arch_pebs_buf_on_cpu(int cpu);
+
+void release_arch_pebs_buf_on_cpu(int cpu);
+
+void init_arch_pebs_on_cpu(int cpu);
+
+void fini_arch_pebs_on_cpu(int cpu);
+
void init_debug_store_on_cpu(int cpu);
void fini_debug_store_on_cpu(int cpu);
diff --git a/arch/x86/include/asm/intel_ds.h b/arch/x86/include/asm/intel_ds.h
index 5dbeac48a5b9..023c2883f9f3 100644
--- a/arch/x86/include/asm/intel_ds.h
+++ b/arch/x86/include/asm/intel_ds.h
@@ -4,7 +4,8 @@
#include <linux/percpu-defs.h>
#define BTS_BUFFER_SIZE (PAGE_SIZE << 4)
-#define PEBS_BUFFER_SIZE (PAGE_SIZE << 4)
+#define PEBS_BUFFER_SHIFT 4
+#define PEBS_BUFFER_SIZE (PAGE_SIZE << PEBS_BUFFER_SHIFT)
/* The maximal number of PEBS events: */
#define MAX_PEBS_EVENTS_FMT4 8
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [Patch v7 10/12] perf/x86/intel: Update dyn_constranit base on PEBS event precise level
2025-08-28 1:34 [Patch v7 00/12] arch-PEBS enabling for Intel platforms Dapeng Mi
` (8 preceding siblings ...)
2025-08-28 1:34 ` [Patch v7 09/12] perf/x86/intel: Allocate arch-PEBS buffer and initialize PEBS_BASE MSR Dapeng Mi
@ 2025-08-28 1:34 ` Dapeng Mi
2025-08-28 1:34 ` [Patch v7 11/12] perf/x86/intel: Setup PEBS data configuration and enable legacy groups Dapeng Mi
` (3 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Dapeng Mi @ 2025-08-28 1:34 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Kan Liang, Andi Kleen, Eranian Stephane
Cc: linux-kernel, linux-perf-users, Dapeng Mi, Dapeng Mi
arch-PEBS provides CPUIDs to enumerate which counters support PEBS
sampling and precise distribution PEBS sampling. Thus PEBS constraints
should be dynamically configured base on these counter and precise
distribution bitmap instead of defining them statically.
Update event dyn_constraint base on PEBS event precise level.
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/intel/core.c | 11 +++++++++++
arch/x86/events/intel/ds.c | 1 +
2 files changed, 12 insertions(+)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 41c4af6bd62c..818c197585c6 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4252,6 +4252,8 @@ static int intel_pmu_hw_config(struct perf_event *event)
}
if (event->attr.precise_ip) {
+ struct arch_pebs_cap pebs_cap = hybrid(event->pmu, arch_pebs_cap);
+
if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT)
return -EINVAL;
@@ -4265,6 +4267,15 @@ static int intel_pmu_hw_config(struct perf_event *event)
}
if (x86_pmu.pebs_aliases)
x86_pmu.pebs_aliases(event);
+
+ if (x86_pmu.arch_pebs) {
+ u64 cntr_mask = hybrid(event->pmu, intel_ctrl) &
+ ~GLOBAL_CTRL_EN_PERF_METRICS;
+ u64 pebs_mask = event->attr.precise_ip >= 3 ?
+ pebs_cap.pdists : pebs_cap.counters;
+ if (cntr_mask != pebs_mask)
+ event->hw.dyn_constraint &= pebs_mask;
+ }
}
if (needs_branch_stack(event)) {
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index ed9bce51182d..4217d0a5d584 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -3022,6 +3022,7 @@ static void __init intel_arch_pebs_init(void)
x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
x86_pmu.drain_pebs = intel_pmu_drain_arch_pebs;
x86_pmu.pebs_capable = ~0ULL;
+ x86_pmu.flags |= PMU_FL_PEBS_ALL;
x86_pmu.pebs_enable = __intel_pmu_pebs_enable;
x86_pmu.pebs_disable = __intel_pmu_pebs_disable;
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [Patch v7 11/12] perf/x86/intel: Setup PEBS data configuration and enable legacy groups
2025-08-28 1:34 [Patch v7 00/12] arch-PEBS enabling for Intel platforms Dapeng Mi
` (9 preceding siblings ...)
2025-08-28 1:34 ` [Patch v7 10/12] perf/x86/intel: Update dyn_constranit base on PEBS event precise level Dapeng Mi
@ 2025-08-28 1:34 ` Dapeng Mi
2025-08-28 1:34 ` [Patch v7 12/12] perf/x86/intel: Add counter group support for arch-PEBS Dapeng Mi
` (2 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Dapeng Mi @ 2025-08-28 1:34 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Kan Liang, Andi Kleen, Eranian Stephane
Cc: linux-kernel, linux-perf-users, Dapeng Mi, Dapeng Mi
Different with legacy PEBS, arch-PEBS provides per-counter PEBS data
configuration by programing MSR IA32_PMC_GPx/FXx_CFG_C MSRs.
This patch obtains PEBS data configuration from event attribute and then
writes the PEBS data configuration to MSR IA32_PMC_GPx/FXx_CFG_C and
enable corresponding PEBS groups.
Please notice this patch only enables XMM SIMD regs sampling for
arch-PEBS, the other SIMD regs (OPMASK/YMM/ZMM) sampling on arch-PEBS
would be supported after PMI based SIMD regs (OPMASK/YMM/ZMM) sampling
is supported.
Co-developed-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/intel/core.c | 136 ++++++++++++++++++++++++++++++-
arch/x86/events/intel/ds.c | 17 ++++
arch/x86/events/perf_event.h | 4 +
arch/x86/include/asm/intel_ds.h | 7 ++
arch/x86/include/asm/msr-index.h | 8 ++
5 files changed, 171 insertions(+), 1 deletion(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 818c197585c6..c8cd490aa539 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -2563,6 +2563,45 @@ static void intel_pmu_disable_fixed(struct perf_event *event)
cpuc->fixed_ctrl_val &= ~mask;
}
+static inline void __intel_pmu_update_event_ext(int idx, u64 ext)
+{
+ struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
+ u32 msr;
+
+ if (idx < INTEL_PMC_IDX_FIXED) {
+ msr = MSR_IA32_PMC_V6_GP0_CFG_C +
+ x86_pmu.addr_offset(idx, false);
+ } else {
+ msr = MSR_IA32_PMC_V6_FX0_CFG_C +
+ x86_pmu.addr_offset(idx - INTEL_PMC_IDX_FIXED, false);
+ }
+
+ cpuc->cfg_c_val[idx] = ext;
+ wrmsrq(msr, ext);
+}
+
+static void intel_pmu_disable_event_ext(struct perf_event *event)
+{
+ if (!x86_pmu.arch_pebs)
+ return;
+
+ /*
+ * Only clear CFG_C MSR for PEBS counter group events,
+ * it avoids the HW counter's value to be added into
+ * other PEBS records incorrectly after PEBS counter
+ * group events are disabled.
+ *
+ * For other events, it's unnecessary to clear CFG_C MSRs
+ * since CFG_C doesn't take effect if counter is in
+ * disabled state. That helps to reduce the WRMSR overhead
+ * in context switches.
+ */
+ if (!is_pebs_counter_event_group(event))
+ return;
+
+ __intel_pmu_update_event_ext(event->hw.idx, 0);
+}
+
static void intel_pmu_disable_event(struct perf_event *event)
{
struct hw_perf_event *hwc = &event->hw;
@@ -2571,9 +2610,12 @@ static void intel_pmu_disable_event(struct perf_event *event)
switch (idx) {
case 0 ... INTEL_PMC_IDX_FIXED - 1:
intel_clear_masks(event, idx);
+ intel_pmu_disable_event_ext(event);
x86_pmu_disable_event(event);
break;
case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
+ intel_pmu_disable_event_ext(event);
+ fallthrough;
case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
intel_pmu_disable_fixed(event);
break;
@@ -2940,6 +2982,66 @@ static void intel_pmu_enable_acr(struct perf_event *event)
DEFINE_STATIC_CALL_NULL(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
+static void intel_pmu_enable_event_ext(struct perf_event *event)
+{
+ struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
+ struct hw_perf_event *hwc = &event->hw;
+ union arch_pebs_index old, new;
+ struct arch_pebs_cap cap;
+ u64 ext = 0;
+
+ if (!x86_pmu.arch_pebs)
+ return;
+
+ cap = hybrid(cpuc->pmu, arch_pebs_cap);
+
+ if (event->attr.precise_ip) {
+ u64 pebs_data_cfg = intel_get_arch_pebs_data_config(event);
+
+ ext |= ARCH_PEBS_EN;
+ if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD)
+ ext |= (-hwc->sample_period) & ARCH_PEBS_RELOAD;
+
+ if (pebs_data_cfg && cap.caps) {
+ if (pebs_data_cfg & PEBS_DATACFG_MEMINFO)
+ ext |= ARCH_PEBS_AUX & cap.caps;
+
+ if (pebs_data_cfg & PEBS_DATACFG_GP)
+ ext |= ARCH_PEBS_GPR & cap.caps;
+
+ if (pebs_data_cfg & PEBS_DATACFG_XMMS)
+ ext |= ARCH_PEBS_VECR_XMM & cap.caps;
+
+ if (pebs_data_cfg & PEBS_DATACFG_LBRS)
+ ext |= ARCH_PEBS_LBR & cap.caps;
+ }
+
+ if (cpuc->n_pebs == cpuc->n_large_pebs)
+ new.thresh = ARCH_PEBS_THRESH_MULTI;
+ else
+ new.thresh = ARCH_PEBS_THRESH_SINGLE;
+
+ rdmsrq(MSR_IA32_PEBS_INDEX, old.whole);
+ if (new.thresh != old.thresh || !old.en) {
+ if (old.thresh == ARCH_PEBS_THRESH_MULTI && old.wr > 0) {
+ /*
+ * Large PEBS was enabled.
+ * Drain PEBS buffer before applying the single PEBS.
+ */
+ intel_pmu_drain_pebs_buffer();
+ } else {
+ new.wr = 0;
+ new.full = 0;
+ new.en = 1;
+ wrmsrq(MSR_IA32_PEBS_INDEX, new.whole);
+ }
+ }
+ }
+
+ if (cpuc->cfg_c_val[hwc->idx] != ext)
+ __intel_pmu_update_event_ext(hwc->idx, ext);
+}
+
static void intel_pmu_enable_event(struct perf_event *event)
{
u64 enable_mask = ARCH_PERFMON_EVENTSEL_ENABLE;
@@ -2955,10 +3057,12 @@ static void intel_pmu_enable_event(struct perf_event *event)
enable_mask |= ARCH_PERFMON_EVENTSEL_BR_CNTR;
intel_set_masks(event, idx);
static_call_cond(intel_pmu_enable_acr_event)(event);
+ intel_pmu_enable_event_ext(event);
__x86_pmu_enable_event(hwc, enable_mask);
break;
case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
static_call_cond(intel_pmu_enable_acr_event)(event);
+ intel_pmu_enable_event_ext(event);
fallthrough;
case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
intel_pmu_enable_fixed(event);
@@ -5301,6 +5405,30 @@ static inline bool intel_pmu_broken_perf_cap(void)
return false;
}
+static inline void __intel_update_pmu_caps(struct pmu *pmu)
+{
+ struct pmu *dest_pmu = pmu ? pmu : x86_get_pmu(smp_processor_id());
+
+ if (hybrid(pmu, arch_pebs_cap).caps & ARCH_PEBS_VECR_XMM)
+ dest_pmu->capabilities |= PERF_PMU_CAP_EXTENDED_REGS;
+}
+
+static inline void __intel_update_large_pebs_flags(struct pmu *pmu)
+{
+ u64 caps = hybrid(pmu, arch_pebs_cap).caps;
+
+ x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME;
+ if (caps & ARCH_PEBS_LBR)
+ x86_pmu.large_pebs_flags |= PERF_SAMPLE_BRANCH_STACK;
+
+ if (!(caps & ARCH_PEBS_AUX))
+ x86_pmu.large_pebs_flags &= ~PERF_SAMPLE_DATA_SRC;
+ if (!(caps & ARCH_PEBS_GPR)) {
+ x86_pmu.large_pebs_flags &=
+ ~(PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER);
+ }
+}
+
static void update_pmu_cap(struct pmu *pmu)
{
unsigned int eax, ebx, ecx, edx;
@@ -5348,8 +5476,12 @@ static void update_pmu_cap(struct pmu *pmu)
hybrid(pmu, arch_pebs_cap).counters = pebs_mask;
hybrid(pmu, arch_pebs_cap).pdists = pdists_mask;
- if (WARN_ON((pebs_mask | pdists_mask) & ~cntrs_mask))
+ if (WARN_ON((pebs_mask | pdists_mask) & ~cntrs_mask)) {
x86_pmu.arch_pebs = 0;
+ } else {
+ __intel_update_pmu_caps(pmu);
+ __intel_update_large_pebs_flags(pmu);
+ }
} else {
WARN_ON(x86_pmu.arch_pebs == 1);
x86_pmu.arch_pebs = 0;
@@ -5513,6 +5645,8 @@ static void intel_pmu_cpu_starting(int cpu)
}
}
+ __intel_update_pmu_caps(cpuc->pmu);
+
if (!cpuc->shared_regs)
return;
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 4217d0a5d584..f62ca4f266d5 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -1528,6 +1528,18 @@ pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc,
}
}
+u64 intel_get_arch_pebs_data_config(struct perf_event *event)
+{
+ u64 pebs_data_cfg = 0;
+
+ if (WARN_ON(event->hw.idx < 0 || event->hw.idx >= X86_PMC_IDX_MAX))
+ return 0;
+
+ pebs_data_cfg |= pebs_update_adaptive_cfg(event);
+
+ return pebs_data_cfg;
+}
+
void intel_pmu_pebs_add(struct perf_event *event)
{
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
@@ -2964,6 +2976,11 @@ static void intel_pmu_drain_arch_pebs(struct pt_regs *iregs,
index.wr = 0;
index.full = 0;
+ index.en = 1;
+ if (cpuc->n_pebs == cpuc->n_large_pebs)
+ index.thresh = ARCH_PEBS_THRESH_MULTI;
+ else
+ index.thresh = ARCH_PEBS_THRESH_SINGLE;
wrmsrq(MSR_IA32_PEBS_INDEX, index.whole);
mask = hybrid(cpuc->pmu, arch_pebs_cap).counters & cpuc->pebs_enabled;
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 13f411bca6bc..3161ec0a3416 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -304,6 +304,8 @@ struct cpu_hw_events {
/* Intel ACR configuration */
u64 acr_cfg_b[X86_PMC_IDX_MAX];
u64 acr_cfg_c[X86_PMC_IDX_MAX];
+ /* Cached CFG_C values */
+ u64 cfg_c_val[X86_PMC_IDX_MAX];
/*
* Intel LBR bits
@@ -1782,6 +1784,8 @@ void intel_pmu_pebs_data_source_cmt(void);
void intel_pmu_pebs_data_source_lnl(void);
+u64 intel_get_arch_pebs_data_config(struct perf_event *event);
+
int intel_pmu_setup_lbr_filter(struct perf_event *event);
void intel_pt_interrupt(void);
diff --git a/arch/x86/include/asm/intel_ds.h b/arch/x86/include/asm/intel_ds.h
index 023c2883f9f3..695f87efbeb8 100644
--- a/arch/x86/include/asm/intel_ds.h
+++ b/arch/x86/include/asm/intel_ds.h
@@ -7,6 +7,13 @@
#define PEBS_BUFFER_SHIFT 4
#define PEBS_BUFFER_SIZE (PAGE_SIZE << PEBS_BUFFER_SHIFT)
+/*
+ * The largest PEBS record could consume a page, ensure
+ * a record at least can be written after triggering PMI.
+ */
+#define ARCH_PEBS_THRESH_MULTI ((PEBS_BUFFER_SIZE - PAGE_SIZE) >> PEBS_BUFFER_SHIFT)
+#define ARCH_PEBS_THRESH_SINGLE 1
+
/* The maximal number of PEBS events: */
#define MAX_PEBS_EVENTS_FMT4 8
#define MAX_PEBS_EVENTS 32
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 7c306dd0713c..737d51629c03 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -330,6 +330,14 @@
#define ARCH_PEBS_OFFSET_MASK 0x7fffff
#define ARCH_PEBS_INDEX_WR_SHIFT 4
+#define ARCH_PEBS_RELOAD 0xffffffff
+#define ARCH_PEBS_LBR_SHIFT 40
+#define ARCH_PEBS_LBR (0x3ull << ARCH_PEBS_LBR_SHIFT)
+#define ARCH_PEBS_VECR_XMM BIT_ULL(49)
+#define ARCH_PEBS_GPR BIT_ULL(61)
+#define ARCH_PEBS_AUX BIT_ULL(62)
+#define ARCH_PEBS_EN BIT_ULL(63)
+
#define MSR_IA32_RTIT_CTL 0x00000570
#define RTIT_CTL_TRACEEN BIT(0)
#define RTIT_CTL_CYCLEACC BIT(1)
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [Patch v7 12/12] perf/x86/intel: Add counter group support for arch-PEBS
2025-08-28 1:34 [Patch v7 00/12] arch-PEBS enabling for Intel platforms Dapeng Mi
` (10 preceding siblings ...)
2025-08-28 1:34 ` [Patch v7 11/12] perf/x86/intel: Setup PEBS data configuration and enable legacy groups Dapeng Mi
@ 2025-08-28 1:34 ` Dapeng Mi
2025-09-19 5:55 ` [Patch v7 00/12] arch-PEBS enabling for Intel platforms Mi, Dapeng
2025-10-09 8:35 ` Mi, Dapeng
13 siblings, 0 replies; 22+ messages in thread
From: Dapeng Mi @ 2025-08-28 1:34 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Kan Liang, Andi Kleen, Eranian Stephane
Cc: linux-kernel, linux-perf-users, Dapeng Mi, Dapeng Mi
Base on previous adaptive PEBS counter snapshot support, add counter
group support for architectural PEBS. Since arch-PEBS shares same
counter group layout with adaptive PEBS, directly reuse
__setup_pebs_counter_group() helper to process arch-PEBS counter group.
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/intel/core.c | 38 ++++++++++++++++++++++++++++---
arch/x86/events/intel/ds.c | 29 ++++++++++++++++++++---
arch/x86/include/asm/msr-index.h | 6 +++++
arch/x86/include/asm/perf_event.h | 13 ++++++++---
4 files changed, 77 insertions(+), 9 deletions(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index c8cd490aa539..52bf3b4bc938 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3014,6 +3014,17 @@ static void intel_pmu_enable_event_ext(struct perf_event *event)
if (pebs_data_cfg & PEBS_DATACFG_LBRS)
ext |= ARCH_PEBS_LBR & cap.caps;
+
+ if (pebs_data_cfg &
+ (PEBS_DATACFG_CNTR_MASK << PEBS_DATACFG_CNTR_SHIFT))
+ ext |= ARCH_PEBS_CNTR_GP & cap.caps;
+
+ if (pebs_data_cfg &
+ (PEBS_DATACFG_FIX_MASK << PEBS_DATACFG_FIX_SHIFT))
+ ext |= ARCH_PEBS_CNTR_FIXED & cap.caps;
+
+ if (pebs_data_cfg & PEBS_DATACFG_METRICS)
+ ext |= ARCH_PEBS_CNTR_METRICS & cap.caps;
}
if (cpuc->n_pebs == cpuc->n_large_pebs)
@@ -3038,6 +3049,9 @@ static void intel_pmu_enable_event_ext(struct perf_event *event)
}
}
+ if (is_pebs_counter_event_group(event))
+ ext |= ARCH_PEBS_CNTR_ALLOW;
+
if (cpuc->cfg_c_val[hwc->idx] != ext)
__intel_pmu_update_event_ext(hwc->idx, ext);
}
@@ -4323,6 +4337,20 @@ static bool intel_pmu_is_acr_group(struct perf_event *event)
return false;
}
+static inline bool intel_pmu_has_pebs_counter_group(struct pmu *pmu)
+{
+ u64 caps;
+
+ if (x86_pmu.intel_cap.pebs_format >= 6 && x86_pmu.intel_cap.pebs_baseline)
+ return true;
+
+ caps = hybrid(pmu, arch_pebs_cap).caps;
+ if (x86_pmu.arch_pebs && (caps & ARCH_PEBS_CNTR_MASK))
+ return true;
+
+ return false;
+}
+
static inline void intel_pmu_set_acr_cntr_constr(struct perf_event *event,
u64 *cause_mask, int *num)
{
@@ -4471,8 +4499,7 @@ static int intel_pmu_hw_config(struct perf_event *event)
}
if ((event->attr.sample_type & PERF_SAMPLE_READ) &&
- (x86_pmu.intel_cap.pebs_format >= 6) &&
- x86_pmu.intel_cap.pebs_baseline &&
+ intel_pmu_has_pebs_counter_group(event->pmu) &&
is_sampling_event(event) &&
event->attr.precise_ip)
event->group_leader->hw.flags |= PERF_X86_EVENT_PEBS_CNTR;
@@ -5420,6 +5447,8 @@ static inline void __intel_update_large_pebs_flags(struct pmu *pmu)
x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME;
if (caps & ARCH_PEBS_LBR)
x86_pmu.large_pebs_flags |= PERF_SAMPLE_BRANCH_STACK;
+ if (caps & ARCH_PEBS_CNTR_MASK)
+ x86_pmu.large_pebs_flags |= PERF_SAMPLE_READ;
if (!(caps & ARCH_PEBS_AUX))
x86_pmu.large_pebs_flags &= ~PERF_SAMPLE_DATA_SRC;
@@ -7133,8 +7162,11 @@ __init int intel_pmu_init(void)
* Many features on and after V6 require dynamic constraint,
* e.g., Arch PEBS, ACR.
*/
- if (version >= 6)
+ if (version >= 6) {
x86_pmu.flags |= PMU_FL_DYN_CONSTRAINT;
+ x86_pmu.late_setup = intel_pmu_late_setup;
+ }
+
/*
* Install the hw-cache-events table:
*/
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index f62ca4f266d5..65908880f424 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -1530,13 +1530,20 @@ pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc,
u64 intel_get_arch_pebs_data_config(struct perf_event *event)
{
+ struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
u64 pebs_data_cfg = 0;
+ u64 cntr_mask;
if (WARN_ON(event->hw.idx < 0 || event->hw.idx >= X86_PMC_IDX_MAX))
return 0;
pebs_data_cfg |= pebs_update_adaptive_cfg(event);
+ cntr_mask = (PEBS_DATACFG_CNTR_MASK << PEBS_DATACFG_CNTR_SHIFT) |
+ (PEBS_DATACFG_FIX_MASK << PEBS_DATACFG_FIX_SHIFT) |
+ PEBS_DATACFG_CNTR | PEBS_DATACFG_METRICS;
+ pebs_data_cfg |= cpuc->pebs_data_cfg & cntr_mask;
+
return pebs_data_cfg;
}
@@ -2441,6 +2448,24 @@ static void setup_arch_pebs_sample_data(struct perf_event *event,
}
}
+ if (header->cntr) {
+ struct arch_pebs_cntr_header *cntr = next_record;
+ unsigned int nr;
+
+ next_record += sizeof(struct arch_pebs_cntr_header);
+
+ if (is_pebs_counter_event_group(event)) {
+ __setup_pebs_counter_group(cpuc, event,
+ (struct pebs_cntr_header *)cntr, next_record);
+ data->sample_flags |= PERF_SAMPLE_READ;
+ }
+
+ nr = hweight32(cntr->cntr) + hweight32(cntr->fixed);
+ if (cntr->metrics == INTEL_CNTR_METRICS)
+ nr += 2;
+ next_record += nr * sizeof(u64);
+ }
+
/* Parse followed fragments if there are. */
if (arch_pebs_record_continued(header)) {
at = at + header->size;
@@ -3111,10 +3136,8 @@ static void __init intel_ds_pebs_init(void)
break;
case 6:
- if (x86_pmu.intel_cap.pebs_baseline) {
+ if (x86_pmu.intel_cap.pebs_baseline)
x86_pmu.large_pebs_flags |= PERF_SAMPLE_READ;
- x86_pmu.late_setup = intel_pmu_late_setup;
- }
fallthrough;
case 5:
x86_pmu.pebs_ept = 1;
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 737d51629c03..41852e8690d7 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -331,12 +331,18 @@
#define ARCH_PEBS_INDEX_WR_SHIFT 4
#define ARCH_PEBS_RELOAD 0xffffffff
+#define ARCH_PEBS_CNTR_ALLOW BIT_ULL(35)
+#define ARCH_PEBS_CNTR_GP BIT_ULL(36)
+#define ARCH_PEBS_CNTR_FIXED BIT_ULL(37)
+#define ARCH_PEBS_CNTR_METRICS BIT_ULL(38)
#define ARCH_PEBS_LBR_SHIFT 40
#define ARCH_PEBS_LBR (0x3ull << ARCH_PEBS_LBR_SHIFT)
#define ARCH_PEBS_VECR_XMM BIT_ULL(49)
#define ARCH_PEBS_GPR BIT_ULL(61)
#define ARCH_PEBS_AUX BIT_ULL(62)
#define ARCH_PEBS_EN BIT_ULL(63)
+#define ARCH_PEBS_CNTR_MASK (ARCH_PEBS_CNTR_GP | ARCH_PEBS_CNTR_FIXED | \
+ ARCH_PEBS_CNTR_METRICS)
#define MSR_IA32_RTIT_CTL 0x00000570
#define RTIT_CTL_TRACEEN BIT(0)
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 3b3848f0d339..7276ba70c88a 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -141,16 +141,16 @@
#define ARCH_PERFMON_EVENTS_COUNT 7
#define PEBS_DATACFG_MEMINFO BIT_ULL(0)
-#define PEBS_DATACFG_GP BIT_ULL(1)
+#define PEBS_DATACFG_GP BIT_ULL(1)
#define PEBS_DATACFG_XMMS BIT_ULL(2)
#define PEBS_DATACFG_LBRS BIT_ULL(3)
-#define PEBS_DATACFG_LBR_SHIFT 24
#define PEBS_DATACFG_CNTR BIT_ULL(4)
+#define PEBS_DATACFG_METRICS BIT_ULL(5)
+#define PEBS_DATACFG_LBR_SHIFT 24
#define PEBS_DATACFG_CNTR_SHIFT 32
#define PEBS_DATACFG_CNTR_MASK GENMASK_ULL(15, 0)
#define PEBS_DATACFG_FIX_SHIFT 48
#define PEBS_DATACFG_FIX_MASK GENMASK_ULL(7, 0)
-#define PEBS_DATACFG_METRICS BIT_ULL(5)
/* Steal the highest bit of pebs_data_cfg for SW usage */
#define PEBS_UPDATE_DS_SW BIT_ULL(63)
@@ -603,6 +603,13 @@ struct arch_pebs_lbr_header {
u64 ler_info;
};
+struct arch_pebs_cntr_header {
+ u32 cntr;
+ u32 fixed;
+ u32 metrics;
+ u32 reserved;
+};
+
/*
* AMD Extended Performance Monitoring and Debug cpuid feature detection
*/
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [Patch v7 00/12] arch-PEBS enabling for Intel platforms
2025-08-28 1:34 [Patch v7 00/12] arch-PEBS enabling for Intel platforms Dapeng Mi
` (11 preceding siblings ...)
2025-08-28 1:34 ` [Patch v7 12/12] perf/x86/intel: Add counter group support for arch-PEBS Dapeng Mi
@ 2025-09-19 5:55 ` Mi, Dapeng
2025-10-09 8:35 ` Mi, Dapeng
13 siblings, 0 replies; 22+ messages in thread
From: Mi, Dapeng @ 2025-09-19 5:55 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Kan Liang, Andi Kleen, Eranian Stephane
Cc: linux-kernel, linux-perf-users, Dapeng Mi
On 8/28/2025 9:34 AM, Dapeng Mi wrote:
> Changes:
> v6 -> v7:
> * Rebase code to last tip perf/core tree.
> * Opportunistically remove the redundant is_x86_event() prototype.
> (Patch 01/12)
> * Fix PEBS handler NULL event access and record loss issue.
> (Patch 02/12)
> * Reset MSR_IA32_PEBS_INDEX at the head of_drain_arch_pebs() instead
> of end. It avoids the processed PEBS records are processed again in
> some corner cases like event throttling. (Patch 08/12)
>
> v5 -> v6:
> * Rebase code to last tip perf/core tree + "x86 perf bug fixes and
> optimization" patchset
>
> v4 -> v5:
> * Rebase code to 6.16-rc3
> * Allocate/free arch-PEBS buffer in callbacks *prepare_cpu/*dead_cpu
> (patch 07/10, Peter)
> * Code and comments refine (patch 09/10, Peter)
>
>
> This patchset introduces architectural PEBS support for Intel platforms
> like Clearwater Forest (CWF) and Panther Lake (PTL). The detailed
> information about arch-PEBS can be found in chapter 11
> "architectural PEBS" of "Intel Architecture Instruction Set Extensions
> and Future Features".
>
> This patch set doesn't include the SSP and SIMD regs (OPMASK/YMM/ZMM)
> sampling support for arch-PEBS to avoid the dependency for the basic
> SIMD regs sampling support patch series[1]. Once the basic SIMD regs
> sampling is supported, the arch-PEBS based SSP and SIMD regs
> (OPMASK/YMM/ZMM) sampling would be supported in a later patch set.
Kindly ping.
Hi Peter,
May I know your comments on this patch series? Is it ok to merge this basic
arch-PEBS enabling patch series first (without SIMD regs sampling support)?
Is there other new comments about this patch set? Thanks.
>
> Tests:
> Run below tests on Clearwater Forest and Pantherlake, no issue is
> found.
>
> 1. Basic perf counting case.
> perf stat -e '{branches,branches,branches,branches,branches,branches,branches,branches,cycles,instructions,ref-cycles}' sleep 1
>
> 2. Basic PMI based perf sampling case.
> perf record -e '{branches,branches,branches,branches,branches,branches,branches,branches,cycles,instructions,ref-cycles}' sleep 1
>
> 3. Basic PEBS based perf sampling case.
> perf record -e '{branches,branches,branches,branches,branches,branches,branches,branches,cycles,instructions,ref-cycles}:p' sleep 1
>
> 4. PEBS sampling case with basic, GPRs, vector-registers and LBR groups
> perf record -e branches:p -Iax,bx,ip,xmm0 -b -c 10000 sleep 1
>
> 5. User space PEBS sampling case with basic, GPRs and LBR groups
> perf record -e branches:p --user-regs=ax,bx,ip -b -c 10000 sleep 1
>
> 6. PEBS sampling case with auxiliary (memory info) group
> perf mem record sleep 1
>
> 7. PEBS sampling case with counter group
> perf record -e '{branches:p,branches,cycles}:S' -c 10000 sleep 1
>
> 8. Perf stat and record test
> perf test 100; perf test 131
>
>
> History:
> v6: https://lore.kernel.org/all/20250821035805.159494-1-dapeng1.mi@linux.intel.com/
> v5: https://lore.kernel.org/all/20250623223546.112465-1-dapeng1.mi@linux.intel.com/
> v4: https://lore.kernel.org/all/20250620103909.1586595-1-dapeng1.mi@linux.intel.com/
> v3: https://lore.kernel.org/all/20250415114428.341182-1-dapeng1.mi@linux.intel.com/
> v2: https://lore.kernel.org/all/20250218152818.158614-1-dapeng1.mi@linux.intel.com/
> v1: https://lore.kernel.org/all/20250123140721.2496639-1-dapeng1.mi@linux.intel.com/
>
> Ref:
> [1]: https://lore.kernel.org/all/20250815213435.1702022-1-kan.liang@linux.intel.com/
>
> Dapeng Mi (12):
> perf/x86: Remove redundant is_x86_event() prototype
> perf/x86/intel: Fix NULL event access and potential PEBS record loss
> perf/x86/intel: Replace x86_pmu.drain_pebs calling with static call
> perf/x86/intel: Correct large PEBS flag check
> perf/x86/intel: Initialize architectural PEBS
> perf/x86/intel/ds: Factor out PEBS record processing code to functions
> perf/x86/intel/ds: Factor out PEBS group processing code to functions
> perf/x86/intel: Process arch-PEBS records or record fragments
> perf/x86/intel: Allocate arch-PEBS buffer and initialize PEBS_BASE MSR
> perf/x86/intel: Update dyn_constranit base on PEBS event precise level
> perf/x86/intel: Setup PEBS data configuration and enable legacy groups
> perf/x86/intel: Add counter group support for arch-PEBS
>
> arch/x86/events/core.c | 21 +-
> arch/x86/events/intel/core.c | 268 ++++++++++++-
> arch/x86/events/intel/ds.c | 621 +++++++++++++++++++++++++-----
> arch/x86/events/perf_event.h | 41 +-
> arch/x86/include/asm/intel_ds.h | 10 +-
> arch/x86/include/asm/msr-index.h | 20 +
> arch/x86/include/asm/perf_event.h | 116 +++++-
> 7 files changed, 955 insertions(+), 142 deletions(-)
>
>
> base-commit: f49e1be19542487921e82b29004908966cb99d7c
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [Patch v7 00/12] arch-PEBS enabling for Intel platforms
2025-08-28 1:34 [Patch v7 00/12] arch-PEBS enabling for Intel platforms Dapeng Mi
` (12 preceding siblings ...)
2025-09-19 5:55 ` [Patch v7 00/12] arch-PEBS enabling for Intel platforms Mi, Dapeng
@ 2025-10-09 8:35 ` Mi, Dapeng
13 siblings, 0 replies; 22+ messages in thread
From: Mi, Dapeng @ 2025-10-09 8:35 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Kan Liang, Andi Kleen, Eranian Stephane
Cc: linux-kernel, linux-perf-users, Dapeng Mi
On 8/28/2025 9:34 AM, Dapeng Mi wrote:
> Changes:
> v6 -> v7:
> * Rebase code to last tip perf/core tree.
> * Opportunistically remove the redundant is_x86_event() prototype.
> (Patch 01/12)
> * Fix PEBS handler NULL event access and record loss issue.
> (Patch 02/12)
> * Reset MSR_IA32_PEBS_INDEX at the head of_drain_arch_pebs() instead
> of end. It avoids the processed PEBS records are processed again in
> some corner cases like event throttling. (Patch 08/12)
Hi Peter,
Do you have more comments on this arch-PEBS enabling patch-set? Thanks.
(The warning raised by kernel test robot about patch 02/12 would be fixed
in next version.)
>
> v5 -> v6:
> * Rebase code to last tip perf/core tree + "x86 perf bug fixes and
> optimization" patchset
>
> v4 -> v5:
> * Rebase code to 6.16-rc3
> * Allocate/free arch-PEBS buffer in callbacks *prepare_cpu/*dead_cpu
> (patch 07/10, Peter)
> * Code and comments refine (patch 09/10, Peter)
>
>
> This patchset introduces architectural PEBS support for Intel platforms
> like Clearwater Forest (CWF) and Panther Lake (PTL). The detailed
> information about arch-PEBS can be found in chapter 11
> "architectural PEBS" of "Intel Architecture Instruction Set Extensions
> and Future Features".
>
> This patch set doesn't include the SSP and SIMD regs (OPMASK/YMM/ZMM)
> sampling support for arch-PEBS to avoid the dependency for the basic
> SIMD regs sampling support patch series[1]. Once the basic SIMD regs
> sampling is supported, the arch-PEBS based SSP and SIMD regs
> (OPMASK/YMM/ZMM) sampling would be supported in a later patch set.
>
> Tests:
> Run below tests on Clearwater Forest and Pantherlake, no issue is
> found.
>
> 1. Basic perf counting case.
> perf stat -e '{branches,branches,branches,branches,branches,branches,branches,branches,cycles,instructions,ref-cycles}' sleep 1
>
> 2. Basic PMI based perf sampling case.
> perf record -e '{branches,branches,branches,branches,branches,branches,branches,branches,cycles,instructions,ref-cycles}' sleep 1
>
> 3. Basic PEBS based perf sampling case.
> perf record -e '{branches,branches,branches,branches,branches,branches,branches,branches,cycles,instructions,ref-cycles}:p' sleep 1
>
> 4. PEBS sampling case with basic, GPRs, vector-registers and LBR groups
> perf record -e branches:p -Iax,bx,ip,xmm0 -b -c 10000 sleep 1
>
> 5. User space PEBS sampling case with basic, GPRs and LBR groups
> perf record -e branches:p --user-regs=ax,bx,ip -b -c 10000 sleep 1
>
> 6. PEBS sampling case with auxiliary (memory info) group
> perf mem record sleep 1
>
> 7. PEBS sampling case with counter group
> perf record -e '{branches:p,branches,cycles}:S' -c 10000 sleep 1
>
> 8. Perf stat and record test
> perf test 100; perf test 131
>
>
> History:
> v6: https://lore.kernel.org/all/20250821035805.159494-1-dapeng1.mi@linux.intel.com/
> v5: https://lore.kernel.org/all/20250623223546.112465-1-dapeng1.mi@linux.intel.com/
> v4: https://lore.kernel.org/all/20250620103909.1586595-1-dapeng1.mi@linux.intel.com/
> v3: https://lore.kernel.org/all/20250415114428.341182-1-dapeng1.mi@linux.intel.com/
> v2: https://lore.kernel.org/all/20250218152818.158614-1-dapeng1.mi@linux.intel.com/
> v1: https://lore.kernel.org/all/20250123140721.2496639-1-dapeng1.mi@linux.intel.com/
>
> Ref:
> [1]: https://lore.kernel.org/all/20250815213435.1702022-1-kan.liang@linux.intel.com/
>
> Dapeng Mi (12):
> perf/x86: Remove redundant is_x86_event() prototype
> perf/x86/intel: Fix NULL event access and potential PEBS record loss
> perf/x86/intel: Replace x86_pmu.drain_pebs calling with static call
> perf/x86/intel: Correct large PEBS flag check
> perf/x86/intel: Initialize architectural PEBS
> perf/x86/intel/ds: Factor out PEBS record processing code to functions
> perf/x86/intel/ds: Factor out PEBS group processing code to functions
> perf/x86/intel: Process arch-PEBS records or record fragments
> perf/x86/intel: Allocate arch-PEBS buffer and initialize PEBS_BASE MSR
> perf/x86/intel: Update dyn_constranit base on PEBS event precise level
> perf/x86/intel: Setup PEBS data configuration and enable legacy groups
> perf/x86/intel: Add counter group support for arch-PEBS
>
> arch/x86/events/core.c | 21 +-
> arch/x86/events/intel/core.c | 268 ++++++++++++-
> arch/x86/events/intel/ds.c | 621 +++++++++++++++++++++++++-----
> arch/x86/events/perf_event.h | 41 +-
> arch/x86/include/asm/intel_ds.h | 10 +-
> arch/x86/include/asm/msr-index.h | 20 +
> arch/x86/include/asm/perf_event.h | 116 +++++-
> 7 files changed, 955 insertions(+), 142 deletions(-)
>
>
> base-commit: f49e1be19542487921e82b29004908966cb99d7c
^ permalink raw reply [flat|nested] 22+ messages in thread