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Subject: Re: [PATCH v9 0/8] Add support for HiSilicon PCIe Tune and Trace
 device
To:     <mark.rutland@arm.com>, <mathieu.poirier@linaro.org>,
        <suzuki.poulose@arm.com>, Peter Zijlstra <peterz@infradead.org>
References: <20220606115555.41103-1-yangyicong@hisilicon.com>
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 <e737393a-56dd-7d24-33d3-e935b14ba758@huawei.com>
 <Yrm4O+AFbgnoBVba@hirez.programming.kicks-ass.net>
From:   Yicong Yang <yangyicong@huawei.com>
Message-ID: <6c923b13-a588-9511-3f94-3241c8aacac5@huawei.com>
Date:   Tue, 28 Jun 2022 15:17:15 +0800
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On 2022/6/27 22:01, Peter Zijlstra wrote:
> On Mon, Jun 27, 2022 at 09:25:42PM +0800, Yicong Yang wrote:
>> On 2022/6/27 21:12, Greg KH wrote:
>>> On Mon, Jun 27, 2022 at 07:18:12PM +0800, Yicong Yang wrote:
>>>> Hi Greg,
>>>>
>>>> Since the kernel side of this device has been reviewed for 8 versions with
>>>> all comments addressed and no more comment since v9 posted in 5.19-rc1,
>>>> is it ok to merge it first (for Patch 1-3 and 7-8)?
>>>
>>> I am not the maintainer of this subsystem, so I do not understand why
>>> you are asking me :(
>>>
>>
>> I checked the log of drivers/hwtracing and seems patches of coresight/intel_th/stm
>> applied by different maintainers and I see you applied some patches of intel_th/stm.
>> Should any of these three maintainers or you can help applied this?
> 
> I was hoping Mark would have a look, since he knows this ARM stuff
> better than me. But ISTR he's somewhat busy atm too. But an ACK from the
> CoreSight people would also be appreciated.
> 

Thanks for the instruction.

Hi Mark, Mathieu and Suzuki,

May I have an ack from you to have the driver part of this device merged?

Thanks!