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X-CSE-ConnectionGUID: cdgvioXrT7+2akBqUM54zg== X-CSE-MsgGUID: qb7PpgVARCChTIa599eiZw== X-IronPort-AV: E=McAfee;i="6800,10657,11612"; a="65243689" X-IronPort-AV: E=Sophos;i="6.19,302,1754982000"; d="scan'208";a="65243689" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2025 10:20:31 -0800 X-CSE-ConnectionGUID: +nko5Ir0SgaPEbP1Ndp03g== X-CSE-MsgGUID: UdlA+nJBQZandO7u60GayQ== X-ExtLoop1: 1 Received: from aschofie-mobl2.amr.corp.intel.com (HELO [10.125.108.136]) ([10.125.108.136]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2025 10:20:31 -0800 Message-ID: <6e84a532-5d30-487f-b849-84893ac2a652@intel.com> Date: Thu, 13 Nov 2025 10:20:31 -0800 Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] x86/events/intel/cstate: Add Pantherlake support To: "Kumar, Kaushlendra" , "mingo@redhat.com" , "acme@kernel.org" , "namhyung@kernel.org" , "jolsa@kernel.org" , "Hunter, Adrian" , "bp@alien8.de" , "dave.hansen@linux.intel.com" , "x86@kernel.org" Cc: "linux-perf-users@vger.kernel.org" , "linux-kernel@vger.kernel.org" References: <20251112090024.3298186-1-kaushlendra.kumar@intel.com> <1ba407b6-a108-41ce-b1b2-3c03aa25d272@intel.com> From: Dave Hansen Content-Language: en-US Autocrypt: addr=dave.hansen@intel.com; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 11/12/25 20:05, Kumar, Kaushlendra wrote: > On 11/12/25, [Reviewer Name] wrote: >> On 11/12/25 01:00, Kaushlendra Kumar wrote: >>> It supports the same C-state residency counters as >>> Lunarlake.This enables monitoring of C1, C6, C7 core states and >>> C2,C3,C6,C10 package states residency counters on Pantherlake >>> platforms. >> >> Is this actually documented? Or is there just a smoke-filled room >> at Intel somewhere where this is decided? > > Good point. Baseline for Pantherlake is Lunarlake with respect to C > states. It is documented in internal documents. This approach is > consistent with similar implementations throughout the kernel > codebase for related CPU families. It needs to be publicly documented somewhere. It doesn't have to be fancy: a web page or white paper would be fine. I know it's been allowed to slide up until now. But, according to[1]: We (Intel) continuously improve, enabling us to be more curious, bold and innovative. So, can we try to improve this, please? ...>> Also, why *can't* this just be enumerated? > > Could you clarify what you mean by "enumerated"? Are you suggesting: > 1. Runtime detection instead of static matching? > 2. A different approach to CPU model matching? > 3. Something else? > > The current approach follows the established pattern for other Intel > CPU models in this driver. If there's a preferred alternative approach, > I'm happy to implement it. Your patch effectively says: PTL supports C10 package states residency counters (among others of course). Why can't there be a bit in CPUID or an MSR somewhere that, when set, means the same thing? That way, we don't have to keep patching the kernel every time there's a new CPU model. I guess in general PMU things haven't been architectural. But this seems like something that wouldn't be too hard for the CPU itself to enumerate to software. 1. https://www.intel.com/content/www/us/en/corporate-responsibility/our-values.html