[PATCH] perf/x86/zhaoxin: Add Yongfeng support

[PATCH] perf/x86/zhaoxin: Add Yongfeng support

[silviazhao]

Add support for Yongfeng which is Zhaoxin's successor microarchitecture
to ZXE.

Remove PERF_COUNT_HW_CACHE_REFERENCES and PERF_COUNT_HW_CACHE_MISSES
from global zx_pmon_event_map, since the cache hierarchy was changed
from Yongfeng, and these pmc event map changed too.

Add PERF_COUNT_HW_BRANCH_INSTRUCTIONS and PERF_COUNT_HW_BRANCH_MISSES
to global zx_pmon_event_map, since these two event will keep consistent
for ZXE and later.

Signed-off-by: silviazhao <silviazhao-oc@zhaoxin.com>
---
 arch/x86/events/zhaoxin/core.c | 29 ++++++++++++++++++++++++-----
 1 file changed, 24 insertions(+), 5 deletions(-)

diff --git a/arch/x86/events/zhaoxin/core.c b/arch/x86/events/zhaoxin/core.c
index 3e9acdaeed1e..06a0923a9581 100644
--- a/arch/x86/events/zhaoxin/core.c
+++ b/arch/x86/events/zhaoxin/core.c
@@ -19,15 +19,15 @@
 #include "../perf_event.h"
 
 /*
- * Zhaoxin PerfMon, used on zxc and later.
+ * Zhaoxin PerfMon, used on ZXE and later.
  */
 static u64 zx_pmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = {
 
 	[PERF_COUNT_HW_CPU_CYCLES]        = 0x0082,
 	[PERF_COUNT_HW_INSTRUCTIONS]      = 0x00c0,
-	[PERF_COUNT_HW_CACHE_REFERENCES]  = 0x0515,
-	[PERF_COUNT_HW_CACHE_MISSES]      = 0x051a,
 	[PERF_COUNT_HW_BUS_CYCLES]        = 0x0083,
+	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x0028,
+	[PERF_COUNT_HW_BRANCH_MISSES]	= 0x0029,
 };
 
 static struct event_constraint zxc_event_constraints[] __read_mostly = {
@@ -559,6 +559,8 @@ __init int zhaoxin_pmu_init(void)
 			zx_pmon_event_map[PERF_COUNT_HW_CACHE_REFERENCES] = 0;
 			zx_pmon_event_map[PERF_COUNT_HW_CACHE_MISSES] = 0;
 			zx_pmon_event_map[PERF_COUNT_HW_BUS_CYCLES] = 0;
+			zx_pmon_event_map[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0;
+			zx_pmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0;
 
 			pr_cont("ZXC events, ");
 			break;
@@ -579,6 +581,9 @@ __init int zhaoxin_pmu_init(void)
 
 			x86_pmu.event_constraints = zxd_event_constraints;
 
+			zx_pmon_event_map[PERF_COUNT_HW_CACHE_REFERENCES]  = 0x0515,
+			zx_pmon_event_map[PERF_COUNT_HW_CACHE_MISSES]      = 0x051a,
+
 			zx_pmon_event_map[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x0700;
 			zx_pmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x0709;
 
@@ -590,11 +595,25 @@ __init int zhaoxin_pmu_init(void)
 
 			x86_pmu.event_constraints = zxd_event_constraints;
 
-			zx_pmon_event_map[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x0028;
-			zx_pmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x0029;
+			zx_pmon_event_map[PERF_COUNT_HW_CACHE_REFERENCES]  = 0x0515,
+			zx_pmon_event_map[PERF_COUNT_HW_CACHE_MISSES]      = 0x051a,
 
 			pr_cont("ZXE events, ");
 			break;
+		case 0x5b:
+			zx_pmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
+				X86_CONFIG(.event = 0x02, .umask = 0x01, .inv = 0x01,
+						.cmask = 0x01);
+
+			memcpy(hw_cache_event_ids, zxe_hw_cache_event_ids,
+					sizeof(hw_cache_event_ids));
+
+			x86_pmu.event_constraints = zxd_event_constraints;
+			zx_pmon_event_map[PERF_COUNT_HW_CACHE_REFERENCES]  = 0x051a;
+			zx_pmon_event_map[PERF_COUNT_HW_CACHE_MISSES]      = 0;
+
+			pr_cont("Yongfeng events, ");
+			break;
 		default:
 			return -ENODEV;
 		}
-- 
2.17.1

Re: [PATCH] perf/x86/zhaoxin: Add Yongfeng support

[Dave Hansen]

On 3/15/23 19:16, silviazhao wrote:
> +		case 0x5b:
> +			zx_pmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
> +				X86_CONFIG(.event = 0x02, .umask = 0x01, .inv = 0x01,
> +						.cmask = 0x01);

On the Intel side of x86/ land, we used to have these open-coded
model/family numbers scattered about.  But, a few years ago, we started
populating arch/x86/include/asm/intel-family.h and using those instead.
I think it's been pretty successful.  It's a lot easier to grep for
INTEL_FAM6_NEHALEM_EX than for 0x2E.

Is there a chance we could start doing the same for other CPU vendors?
Perhaps start with:

#define ZHAOXIN_FAMILY_YONGFENG 0x5B

Re: [PATCH] perf/x86/zhaoxin: Add Yongfeng support

[silviazhaooc]

On 2023/3/16 22:59, Dave Hansen wrote:
> On 3/15/23 19:16, silviazhao wrote:
>> +		case 0x5b:
>> +			zx_pmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
>> +				X86_CONFIG(.event = 0x02, .umask = 0x01, .inv = 0x01,
>> +						.cmask = 0x01);
> 
> On the Intel side of x86/ land, we used to have these open-coded
> model/family numbers scattered about.  But, a few years ago, we started
> populating arch/x86/include/asm/intel-family.h and using those instead.
> I think it's been pretty successful.  It's a lot easier to grep for
> INTEL_FAM6_NEHALEM_EX than for 0x2E.
> 
> Is there a chance we could start doing the same for other CPU vendors?
> Perhaps start with:
> 
> #define ZHAOXIN_FAMILY_YONGFENG 0x5B

Great suggestion. After discussing with my colleagues, we decide to add 
these open-coded model/family numbers into a new file like 
zhaoxin-family.h, create a new patch set and re-commit.