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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: LX9jHMgaxJQ68GWlVqA72vcrm1orYwdvNs/SpLmcA3UP6w6p7PHwFUaT1Qh2OQkXPAsj1iFkBTWh19TK01pU4bwlTGNQUOJAp1HAigkhyqTtVKbm/HVAOlW0GmTnsB7wgtuYq87N33PiW9u+/hUxmggbXaEA8DwfK4yJB95WFJ7B78q7r3NjJXdLhQ9BlW7NYxXf5xI3Dej1cMvM5JwPSbubKcgIYlvDe3f40exFtW2E3ppvNKrWpTkSsdgQyPWXCIDSmCYigbWZUtJRh5iT6fdVZuQqyzewb451d2rVSvpBxbqbT/+brUY2avSTNRps6YkXffgPn3nwEapN3dsKY29Qq+/4p8JVpDBPrpOwYfBp6CG30lFKFdxDo70JM2DIGLH+UCGfP2UxebPnJL0IgTw+4d85O9kdyXLZODK73mpmRehxXSQaEBGYTlFQc+42 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2026 04:00:48.3492 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4b2d301b-dd2f-4c4a-dff0-08de99da6978 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000C6185.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS2PR12MB9775 >> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h >> --- a/arch/x86/include/asm/msr-index.h >> +++ b/arch/x86/include/asm/msr-index.h >> @@ -698,6 +698,8 @@ >> #define MSR_AMD64_IBSBRTARGET 0xc001103b >> #define MSR_AMD64_ICIBSEXTDCTL 0xc001103c >> #define MSR_AMD64_IBSOPDATA4 0xc001103d >> +#define MSR_AMD64_IBSOPCTL2 0xc001103e >> +#define MSR_AMD64_IBSFETCHCTL2 0xc001103f >> #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ > > This isn't a regression from the current patch, but looking at the adjacent > MSR handling code, is there a potential stack buffer overflow in the IBS > NMI handler on CPUs supporting IBS_CAPS_OPDATA4? > > In arch/x86/events/amd/ibs.c, struct perf_ibs_data is allocated on the > stack in perf_ibs_handle_irq(). Its regs array is sized using > MSR_AMD64_IBS_REG_COUNT_MAX, which is 8. > > When handling a perf_ibs_op event, the initial read loop fetches up to 7 > MSRs, advancing the pointer buf to &ibs_data.regs[7]. > > Subsequently, the handler reads additional MSRs depending on CPU caps: > > if (event->attr.sample_type & PERF_SAMPLE_RAW) { > if (perf_ibs == &perf_ibs_op) { > if (ibs_caps & IBS_CAPS_BRNTRGT) { > rdmsrq(MSR_AMD64_IBSBRTARGET, *buf++); > br_target_idx = size; > size++; > } > if (ibs_caps & IBS_CAPS_OPDATA4) { > rdmsrq(MSR_AMD64_IBSOPDATA4, *buf++); > size++; > } > } > > If the CPU supports IBS_CAPS_BRNTRGT, MSR_AMD64_IBSBRTARGET is read into > regs[7], advancing buf to ®s[8]. > > If the CPU also supports IBS_CAPS_OPDATA4, it reads MSR_AMD64_IBSOPDATA4 into > the next pointer position, which translates to regs[8]. This writes one > element past the end of the 8-element array, overwriting adjacent local > variables on the stack. > > Furthermore, ibs_data.size is incremented to 9, so > perf_sample_save_raw_data() will subsequently read 72 bytes of regs, > exposing the corrupted stack data to user-space in the raw perf record. Since > unprivileged users can configure RAW IBS events, this might lead to > unintended behavior. > > Should MSR_AMD64_IBS_REG_COUNT_MAX be increased to account for > IBS_CAPS_OPDATA4? Thanks for the bug report. While this seems like a genuine overflow issue, IbsOpData4 has been deprecated from long back. I was unable to find any platform that supports it. So it's not a real a concern. Thanks, Ravi