From: Ravi Bangoria <ravi.bangoria@amd.com>
To: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>,
James Clark <james.clark@linaro.org>, <x86@kernel.org>,
<linux-perf-users@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
"Manali Shukla" <manali.shukla@amd.com>,
Santosh Shukla <santosh.shukla@amd.com>,
Ananth Narayan <ananth.narayan@amd.com>,
Sandipan Das <sandipan.das@amd.com>
Subject: Re: [PATCH 07/11] perf/amd/ibs: Support IBS_{FETCH|OP}_CTL2[Dis] to eliminate RMW race
Date: Mon, 19 Jan 2026 18:30:12 +0530 [thread overview]
Message-ID: <7a012575-bf92-4614-80e7-6bbe593f57cd@amd.com> (raw)
In-Reply-To: <82e836e7-c0cc-4226-91cf-4b2275d99e73@linux.intel.com>
Hi Dapeng,
>> static int x86_pmu_amd_ibs_starting_cpu(unsigned int cpu)
>> {
>> setup_APIC_ibs();
>> +
>> + if (ibs_caps & IBS_CAPS_DIS) {
>> + /*
>> + * IBS enable sequence:
>> + * CTL[En] = 1;
>> + * CTL2[Dis] = 0;
>> + *
>> + * IBS disable sequence:
>> + * CTL2[Dis] = 1;
>> + *
>> + * Set CTL2[Dis] when CPU comes up. This is needed to make
>> + * enable sequence effective.
>> + */
>> + wrmsrq(MSR_AMD64_IBSFETCHCTL2, 1);
>> + wrmsrq(MSR_AMD64_IBSOPCTL2, 1);
>
> What does the BIT 0 of these 2 MSRs mean? Disable? Better define a macro
> instead of using the magic number "1".
Right, those are disable bits. I'll replace those magic numbers with
IBS_FETCH_2_DIS and IBS_OP_2_DIS.
Thanks,
Ravi
next prev parent reply other threads:[~2026-01-19 13:00 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-16 3:34 [PATCH 00/11] perf/amd/ibs: Fixes + future enhancements Ravi Bangoria
2026-01-16 3:34 ` [PATCH 01/11] perf/amd/ibs: Throttle interrupts with filtered ldlat samples Ravi Bangoria
2026-01-19 7:31 ` Mi, Dapeng
2026-01-19 12:56 ` Ravi Bangoria
2026-01-16 3:34 ` [PATCH 02/11] perf/amd/ibs: Limit ldlat->l3missonly dependency to Zen5 Ravi Bangoria
2026-01-16 3:34 ` [PATCH 03/11] perf/amd/ibs: Preserve PhyAddrVal bit when clearing PhyAddr MSR Ravi Bangoria
2026-01-16 3:34 ` [PATCH 04/11] perf/amd/ibs: Avoid race between event add and NMI Ravi Bangoria
2026-01-16 3:34 ` [PATCH 05/11] perf/amd/ibs: Define macro for ldlat mask Ravi Bangoria
2026-01-19 7:38 ` Mi, Dapeng
2026-01-16 3:34 ` [PATCH 06/11] perf/amd/ibs: Add new MSRs and CPUID bits definitions Ravi Bangoria
2026-01-19 7:39 ` Mi, Dapeng
2026-01-16 3:34 ` [PATCH 07/11] perf/amd/ibs: Support IBS_{FETCH|OP}_CTL2[Dis] to eliminate RMW race Ravi Bangoria
2026-01-19 7:48 ` Mi, Dapeng
2026-01-19 13:00 ` Ravi Bangoria [this message]
2026-01-16 3:34 ` [PATCH 08/11] perf/amd/ibs: Enable fetch latency filtering Ravi Bangoria
2026-01-16 3:34 ` [PATCH 09/11] perf/amd/ibs: Enable RIP bit63 hardware filtering Ravi Bangoria
2026-01-16 3:34 ` [PATCH 10/11] perf/amd/ibs: Enable streaming store filter Ravi Bangoria
2026-01-19 7:57 ` Mi, Dapeng
2026-01-19 13:02 ` Ravi Bangoria
2026-01-16 3:34 ` [PATCH 11/11] perf/amd/ibs: Advertise remote socket capability Ravi Bangoria
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