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X-CSE-ConnectionGUID: T4A9ibPHSlasJN8aVk03Ag== X-CSE-MsgGUID: dYA07eNsS6enzt21zDNsag== X-IronPort-AV: E=McAfee;i="6700,10204,11336"; a="56815412" X-IronPort-AV: E=Sophos;i="6.13,263,1732608000"; d="scan'208";a="56815412" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2025 18:26:12 -0800 X-CSE-ConnectionGUID: WIiYFZmXSxS00ld9/ptZCg== X-CSE-MsgGUID: pVMeW+KrR6i9EDcRi5JvcA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="115154167" Received: from dapengmi-mobl1.ccr.corp.intel.com (HELO [10.124.245.128]) ([10.124.245.128]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2025 18:26:02 -0800 Message-ID: <7a03fdf5-f080-4580-8850-20dc88003d14@linux.intel.com> Date: Thu, 6 Feb 2025 10:25:59 +0800 Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 06/20] perf/x86/intel: Initialize architectural PEBS To: Peter Zijlstra Cc: Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Kan Liang , Andi Kleen , Eranian Stephane , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi References: <20250123140721.2496639-1-dapeng1.mi@linux.intel.com> <20250123140721.2496639-7-dapeng1.mi@linux.intel.com> <20250128112202.GA7145@noisy.programming.kicks-ass.net> Content-Language: en-US From: "Mi, Dapeng" In-Reply-To: <20250128112202.GA7145@noisy.programming.kicks-ass.net> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 1/28/2025 7:22 PM, Peter Zijlstra wrote: > On Thu, Jan 23, 2025 at 02:07:07PM +0000, Dapeng Mi wrote: > > >> diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c >> index e8a06c8486af..1b33a6a60584 100644 >> --- a/arch/x86/events/intel/ds.c >> +++ b/arch/x86/events/intel/ds.c >> @@ -1537,6 +1537,9 @@ void intel_pmu_pebs_enable(struct perf_event *event) >> >> cpuc->pebs_enabled |= 1ULL << hwc->idx; >> >> + if (x86_pmu.arch_pebs) >> + return; >> + >> if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) && (x86_pmu.version < 5)) >> cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32); >> else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST) >> @@ -1606,6 +1609,11 @@ void intel_pmu_pebs_disable(struct perf_event *event) >> >> cpuc->pebs_enabled &= ~(1ULL << hwc->idx); >> >> + hwc->config |= ARCH_PERFMON_EVENTSEL_INT; >> + >> + if (x86_pmu.arch_pebs) >> + return; >> + >> if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) && >> (x86_pmu.version < 5)) >> cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32)); >> @@ -1616,15 +1624,13 @@ void intel_pmu_pebs_disable(struct perf_event *event) >> >> if (cpuc->enabled) >> wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); >> - >> - hwc->config |= ARCH_PERFMON_EVENTSEL_INT; >> } >> >> void intel_pmu_pebs_enable_all(void) >> { >> struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); >> >> - if (cpuc->pebs_enabled) >> + if (!x86_pmu.arch_pebs && cpuc->pebs_enabled) >> wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); >> } >> >> @@ -1632,7 +1638,7 @@ void intel_pmu_pebs_disable_all(void) >> { >> struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); >> >> - if (cpuc->pebs_enabled) >> + if (!x86_pmu.arch_pebs && cpuc->pebs_enabled) >> __intel_pmu_pebs_disable_all(); >> } > So there's a ton of if (arch_pebs) sprinkled around. Can't we avoid that > by using a few static_call()s ? Sure. Let me try it.