From: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Jiri Olsa <jolsa@kernel.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Andi Kleen <ak@linux.intel.com>,
Eranian Stephane <eranian@google.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
broonie@kernel.org, Ravi Bangoria <ravi.bangoria@amd.com>,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
Zide Chen <zide.chen@intel.com>,
Falcon Thomas <thomas.falcon@intel.com>,
Dapeng Mi <dapeng1.mi@intel.com>,
Xudong Hao <xudong.hao@intel.com>,
Kan Liang <kan.liang@linux.intel.com>
Subject: Re: [Patch v7 07/24] perf/x86: Introduce x86-specific x86_pmu_setup_regs_data()
Date: Wed, 25 Mar 2026 13:18:44 +0800 [thread overview]
Message-ID: <7efb05b6-ce14-4a55-b45a-fe79872d8fd9@linux.intel.com> (raw)
In-Reply-To: <20260324004118.3772171-8-dapeng1.mi@linux.intel.com>
On 3/24/2026 8:41 AM, Dapeng Mi wrote:
> From: Kan Liang <kan.liang@linux.intel.com>
>
> The current perf/x86 implementation uses the generic functions
> perf_sample_regs_user() and perf_sample_regs_intr() to set up registers
> data for sampling records. While this approach works for general
> registers, it falls short when adding sampling support for SIMD and APX
> eGPRs registers on x86 platforms.
>
> To address this, we introduce the x86-specific function
> x86_pmu_setup_regs_data() for setting up register data on x86 platforms.
>
> At present, x86_pmu_setup_regs_data() mirrors the logic of the generic
> functions perf_sample_regs_user() and perf_sample_regs_intr().
> Subsequent patches will introduce x86-specific enhancements.
>
> Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
> Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
> ---
> arch/x86/events/core.c | 33 +++++++++++++++++++++++++++++++++
> arch/x86/events/intel/ds.c | 9 ++++++---
> arch/x86/events/perf_event.h | 4 ++++
> 3 files changed, 43 insertions(+), 3 deletions(-)
>
> diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
> index ad6cbc19592d..0a6c51e86e9b 100644
> --- a/arch/x86/events/core.c
> +++ b/arch/x86/events/core.c
> @@ -1699,6 +1699,39 @@ static void x86_pmu_del(struct perf_event *event, int flags)
> static_call_cond(x86_pmu_del)(event);
> }
>
> +void x86_pmu_setup_regs_data(struct perf_event *event,
> + struct perf_sample_data *data,
> + struct pt_regs *regs)
> +{
> + struct perf_event_attr *attr = &event->attr;
> + u64 sample_type = attr->sample_type;
> +
> + if (sample_type & PERF_SAMPLE_REGS_USER) {
> + if (user_mode(regs)) {
> + data->regs_user.abi = perf_reg_abi(current);
> + data->regs_user.regs = regs;
> + } else if (!(current->flags & PF_KTHREAD)) {
Sashiko (AI agent) reviews this patchset. I would pick the reasonable
comment and paste here.
"
Is it safe to rely on !(current->flags & PF_KTHREAD) here?
Core perf code replaced this with the is_user_task() helper in commit
76ed27608f7d to prevent crashes. If a task is exiting (where task->mm
is cleared but PF_KTHREAD is not set) or if it is an io_uring thread
(which uses PF_USER_WORKER), could this pass the check and cause a NULL
pointer dereference or leak uninitialized kernel registers to user-space?
"
The comment looks reasonable and would fix it in next version.
> + perf_get_regs_user(&data->regs_user, regs);
> + } else {
> + data->regs_user.abi = PERF_SAMPLE_REGS_ABI_NONE;
> + data->regs_user.regs = NULL;
> + }
> + data->dyn_size += sizeof(u64);
> + if (data->regs_user.regs)
> + data->dyn_size += hweight64(attr->sample_regs_user) * sizeof(u64);
> + data->sample_flags |= PERF_SAMPLE_REGS_USER;
> + }
> +
> + if (sample_type & PERF_SAMPLE_REGS_INTR) {
> + data->regs_intr.regs = regs;
> + data->regs_intr.abi = perf_reg_abi(current);
> + data->dyn_size += sizeof(u64);
> + if (data->regs_intr.regs)
> + data->dyn_size += hweight64(attr->sample_regs_intr) * sizeof(u64);
> + data->sample_flags |= PERF_SAMPLE_REGS_INTR;
> + }
> +}
> +
> int x86_pmu_handle_irq(struct pt_regs *regs)
> {
> struct perf_sample_data data;
> diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
> index 52eb6eac5df3..b045297c02d0 100644
> --- a/arch/x86/events/intel/ds.c
> +++ b/arch/x86/events/intel/ds.c
> @@ -2450,6 +2450,7 @@ static inline void __setup_pebs_basic_group(struct perf_event *event,
> }
>
> static inline void __setup_pebs_gpr_group(struct perf_event *event,
> + struct perf_sample_data *data,
> struct pt_regs *regs,
> struct pebs_gprs *gprs,
> u64 sample_type)
> @@ -2459,8 +2460,10 @@ static inline void __setup_pebs_gpr_group(struct perf_event *event,
> regs->flags &= ~PERF_EFLAGS_EXACT;
> }
>
> - if (sample_type & (PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER))
> + if (sample_type & (PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER)) {
> adaptive_pebs_save_regs(regs, gprs);
> + x86_pmu_setup_regs_data(event, data, regs);
> + }
> }
>
> static inline void __setup_pebs_meminfo_group(struct perf_event *event,
> @@ -2553,7 +2556,7 @@ static void setup_pebs_adaptive_sample_data(struct perf_event *event,
> gprs = next_record;
> next_record = gprs + 1;
>
> - __setup_pebs_gpr_group(event, regs, gprs, sample_type);
> + __setup_pebs_gpr_group(event, data, regs, gprs, sample_type);
> }
>
> if (format_group & PEBS_DATACFG_MEMINFO) {
> @@ -2677,7 +2680,7 @@ static void setup_arch_pebs_sample_data(struct perf_event *event,
> gprs = next_record;
> next_record = gprs + 1;
>
> - __setup_pebs_gpr_group(event, regs,
> + __setup_pebs_gpr_group(event, data, regs,
> (struct pebs_gprs *)gprs,
> sample_type);
> }
> diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
> index fad87d3c8b2c..39c41947c70d 100644
> --- a/arch/x86/events/perf_event.h
> +++ b/arch/x86/events/perf_event.h
> @@ -1306,6 +1306,10 @@ void x86_pmu_enable_event(struct perf_event *event);
>
> int x86_pmu_handle_irq(struct pt_regs *regs);
>
> +void x86_pmu_setup_regs_data(struct perf_event *event,
> + struct perf_sample_data *data,
> + struct pt_regs *regs);
> +
> void x86_pmu_show_pmu_cap(struct pmu *pmu);
>
> static inline int x86_pmu_num_counters(struct pmu *pmu)
next prev parent reply other threads:[~2026-03-25 5:18 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-24 0:40 [Patch v7 00/24] Support SIMD/eGPRs/SSP registers sampling for perf Dapeng Mi
2026-03-24 0:40 ` [Patch v7 01/24] perf/x86: Move hybrid PMU initialization before x86_pmu_starting_cpu() Dapeng Mi
2026-03-24 0:40 ` [Patch v7 02/24] perf/x86/intel: Avoid PEBS event on fixed counters without extended PEBS Dapeng Mi
2026-03-24 0:40 ` [Patch v7 03/24] perf/x86/intel: Enable large PEBS sampling for XMMs Dapeng Mi
2026-03-24 0:40 ` [Patch v7 04/24] perf/x86/intel: Convert x86_perf_regs to per-cpu variables Dapeng Mi
2026-03-24 0:40 ` [Patch v7 05/24] perf: Eliminate duplicate arch-specific functions definations Dapeng Mi
2026-03-24 0:41 ` [Patch v7 06/24] perf/x86: Use x86_perf_regs in the x86 nmi handler Dapeng Mi
2026-03-24 0:41 ` [Patch v7 07/24] perf/x86: Introduce x86-specific x86_pmu_setup_regs_data() Dapeng Mi
2026-03-25 5:18 ` Mi, Dapeng [this message]
2026-03-24 0:41 ` [Patch v7 08/24] x86/fpu/xstate: Add xsaves_nmi() helper Dapeng Mi
2026-03-24 0:41 ` [Patch v7 09/24] x86/fpu: Ensure TIF_NEED_FPU_LOAD is set after saving FPU state Dapeng Mi
2026-03-24 0:41 ` [Patch v7 10/24] perf: Move and rename has_extended_regs() for ARCH-specific use Dapeng Mi
2026-03-24 0:41 ` [Patch v7 11/24] perf/x86: Enable XMM Register Sampling for Non-PEBS Events Dapeng Mi
2026-03-25 7:30 ` Mi, Dapeng
2026-03-24 0:41 ` [Patch v7 12/24] perf/x86: Enable XMM register sampling for REGS_USER case Dapeng Mi
2026-03-25 7:58 ` Mi, Dapeng
2026-03-24 0:41 ` [Patch v7 13/24] perf: Add sampling support for SIMD registers Dapeng Mi
2026-03-25 8:44 ` Mi, Dapeng
2026-03-24 0:41 ` [Patch v7 14/24] perf/x86: Enable XMM sampling using sample_simd_vec_reg_* fields Dapeng Mi
2026-03-25 9:01 ` Mi, Dapeng
2026-03-24 0:41 ` [Patch v7 15/24] perf/x86: Enable YMM " Dapeng Mi
2026-03-24 0:41 ` [Patch v7 16/24] perf/x86: Enable ZMM " Dapeng Mi
2026-03-24 0:41 ` [Patch v7 17/24] perf/x86: Enable OPMASK sampling using sample_simd_pred_reg_* fields Dapeng Mi
2026-03-24 0:41 ` [Patch v7 18/24] perf: Enhance perf_reg_validate() with simd_enabled argument Dapeng Mi
2026-03-24 0:41 ` [Patch v7 19/24] perf/x86: Enable eGPRs sampling using sample_regs_* fields Dapeng Mi
2026-03-24 0:41 ` [Patch v7 20/24] perf/x86: Enable SSP " Dapeng Mi
2026-03-25 9:25 ` Mi, Dapeng
2026-03-24 0:41 ` [Patch v7 21/24] perf/x86/intel: Enable PERF_PMU_CAP_SIMD_REGS capability Dapeng Mi
2026-03-24 0:41 ` [Patch v7 22/24] perf/x86/intel: Enable arch-PEBS based SIMD/eGPRs/SSP sampling Dapeng Mi
2026-03-24 0:41 ` [Patch v7 23/24] perf/x86: Activate back-to-back NMI detection for arch-PEBS induced NMIs Dapeng Mi
2026-03-24 0:41 ` [Patch v7 24/24] perf/x86/intel: Add sanity check for PEBS fragment size Dapeng Mi
2026-03-24 1:08 ` [Patch v7 00/24] Support SIMD/eGPRs/SSP registers sampling for perf Mi, Dapeng
2026-03-25 9:41 ` Mi, Dapeng
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