From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4AEA22D4C9; Thu, 29 May 2025 16:57:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748537847; cv=none; b=uDKrJEHcXgXe3HLoyQ0PqyT+GZyEJRahUNiaYmRSHXz73GwaDog2rpmetxEfWtxwYJTSYBoE47cX+WCDIu7gsGyBaNaf1Qcbi7QQEbvwjuGMyaRXcIgqqMwFj2Myvn7lLcIxk99DEcn1OISb3Z3WhLyMQn4GwaPKbTZ938+7YZ0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748537847; c=relaxed/simple; bh=nTb8EzIrvGiW+oT3lk+HKRBUzG7cl6yVbYX2HGFS1wY=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=LKCq01mz1Wf6m67rBqFMpJj/bBJEyVK+FCQGIGFnQF4Eex0NDw1JqXwVWHWImAvjgqsRO5jgjSJJED9VjDkw9IczpN0I09KSUXkANrwQhtaNDd3KWe7EofJEZ5GFW46K35ixn5UuxlJjPo9wqSPZRHHvSPf0LF69hQm02iskd/8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ocydWOce; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ocydWOce" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3891FC4CEE7; Thu, 29 May 2025 16:57:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1748537847; bh=nTb8EzIrvGiW+oT3lk+HKRBUzG7cl6yVbYX2HGFS1wY=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=ocydWOce2vgQ01StCxi2p8JIr5rtxb48tv1V7H37/y3VwgQFMz/G/OC8MgZFiAdK5 5sLWjC4vr7ThGNaftjRtqwxLh1KmpBBcTMf0i+AzWSa31JT55xS+wPOw5oDF3DXVol +ktqh8a1R+ROKDCVXuT7JR64GyottFxcT+kVzap4ZJkhIqCaTpPsTTFd0I0AIev3hK lucd3K9DUfRO+vtFpXtBcn7uDeTY7FnrI20xUBr1wGCZv0Kykw2nAVn8voYXH0Ykv9 tCNTNoIZAwJpB2bPTqrFoLra/CEEa9dCSMMz016V7PzpTxb0l0pKkNWyY6hOOKxwhU ryg4iHafOGHXw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1uKgZI-001cmR-Ja; Thu, 29 May 2025 17:57:24 +0100 Date: Thu, 29 May 2025 17:57:24 +0100 Message-ID: <865xhje4nf.wl-maz@kernel.org> From: Marc Zyngier To: James Clark Cc: Catalin Marinas , Will Deacon , Mark Rutland , Jonathan Corbet , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev Subject: Re: [PATCH v2 05/11] arm64/boot: Enable EL2 requirements for SPE_FEAT_FDS In-Reply-To: <20250529-james-perf-feat_spe_eft-v2-5-a01a9baad06a@linaro.org> References: <20250529-james-perf-feat_spe_eft-v2-0-a01a9baad06a@linaro.org> <20250529-james-perf-feat_spe_eft-v2-5-a01a9baad06a@linaro.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: james.clark@linaro.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, corbet@lwn.net, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 29 May 2025 12:30:26 +0100, James Clark wrote: > > SPE data source filtering (optional from Armv8.8) requires that traps to > the filter register PMSDSFR be disabled. Document the requirements and > disable the traps if the feature is present. > > Signed-off-by: James Clark > --- > Documentation/arch/arm64/booting.rst | 11 +++++++++++ > arch/arm64/include/asm/el2_setup.h | 14 ++++++++++++++ > 2 files changed, 25 insertions(+) > > diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm64/booting.rst > index dee7b6de864f..abd75085a239 100644 > --- a/Documentation/arch/arm64/booting.rst > +++ b/Documentation/arch/arm64/booting.rst > @@ -404,6 +404,17 @@ Before jumping into the kernel, the following conditions must be met: > - HDFGWTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1. > - HDFGWTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1. > > + For CPUs with SPE data source filtering (FEAT_SPE_FDS): > + > + - If EL3 is present: > + > + - MDCR_EL3.EnPMS3 (bit 42) must be initialised to 0b1. > + > + - If the kernel is entered at EL1 and EL2 is present: > + > + - HDFGRTR2_EL2.nPMSDSFR_EL1 (bit 19) must be initialised to 0b1. > + - HDFGWTR2_EL2.nPMSDSFR_EL1 (bit 19) must be initialised to 0b1. > + > For CPUs with Memory Copy and Memory Set instructions (FEAT_MOPS): > > - If the kernel is entered at EL1 and EL2 is present: > diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h > index f6d72ca03133..6d0d8c25e912 100644 > --- a/arch/arm64/include/asm/el2_setup.h > +++ b/arch/arm64/include/asm/el2_setup.h > @@ -279,6 +279,20 @@ > orr x0, x0, #HDFGRTR2_EL2_nPMICFILTR_EL0 > orr x0, x0, #HDFGRTR2_EL2_nPMUACR_EL1 > .Lskip_pmuv3p9_\@: > + mrs x1, id_aa64dfr0_el1 > + ubfx x1, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4 > + /* If SPE is implemented, */ > + cmp x1, #ID_AA64DFR0_EL1_PMSVer_IMP > + b.lt .Lskip_spefds_\@ > + /* we can read PMSIDR and */ > + mrs_s x1, SYS_PMSIDR_EL1 > + and x1, x1, #(1 << PMSIDR_EL1_FDS_SHIFT) Use PMSIDR_EL1_FDS directly, just like you do for the other register fields. M. -- Without deviation from the norm, progress is not possible.