Re: [PATCH 06/12] perf arm_spe: Add "events" entry in meta data

[James Clark <james.clark@linaro.org>]

On 13/06/2025 4:53 pm, Leo Yan wrote:
> Add a new "events" entry in the meta data and dump it in raw data mode.
> 
> After:
> 
>    # perf script -D
>    ...
> 
>    0 0 0x470 [0x1f0]: PERF_RECORD_AUXTRACE_INFO type: 4
>      Header version     :2
>      Header size        :4
>      PMU type v2        :11
>      CPU number         :8
>        Magic            :0x1010101010101010
>        CPU #            :0
>        Num of params    :4
>        MIDR             :0x410fd0f0
>        PMU Type         :11
>        Min Interval     :256
>        Events           :0xffff000003fefffe
> 

Pending possibly renaming this field on patch 2

Reviewed-by: James Clark <james.clark@linaro.org>


>    ...
> 
> Signed-off-by: Leo Yan <leo.yan@arm.com>
> ---
>   tools/perf/arch/arm64/util/arm-spe.c | 5 +++++
>   tools/perf/util/arm-spe.c            | 1 +
>   tools/perf/util/arm-spe.h            | 2 ++
>   3 files changed, 8 insertions(+)
> 
> diff --git a/tools/perf/arch/arm64/util/arm-spe.c b/tools/perf/arch/arm64/util/arm-spe.c
> index 4f2833b62ff55f3fd1dff3f032d6e06528460939..5cce5f29d8c7936cc4f424a09d50536644c17be9 100644
> --- a/tools/perf/arch/arm64/util/arm-spe.c
> +++ b/tools/perf/arch/arm64/util/arm-spe.c
> @@ -121,12 +121,17 @@ static int arm_spe_save_cpu_header(struct auxtrace_record *itr,
>   		/* No Arm SPE PMU is found */
>   		data[ARM_SPE_CPU_PMU_TYPE] = ULLONG_MAX;
>   		data[ARM_SPE_CAP_MIN_IVAL] = 0;
> +		data[ARM_SPE_CAP_EVENTS] = 0;
>   	} else {
>   		data[ARM_SPE_CPU_PMU_TYPE] = pmu->type;
>   
>   		if (perf_pmu__scan_file(pmu, "caps/min_interval", "%lu", &val) != 1)
>   			val = 0;
>   		data[ARM_SPE_CAP_MIN_IVAL] = val;
> +
> +		if (perf_pmu__scan_file(pmu, "caps/events", "%lu", &val) != 1)
> +			val = 0;
> +		data[ARM_SPE_CAP_EVENTS] = val;
>   	}
>   
>   	free(cpuid);
> diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c
> index fdef6f743cf3c76b1dcdd57f5a2c297642fdd21a..55b8391990467c8b7818bb63de3545d94d021bb7 100644
> --- a/tools/perf/util/arm-spe.c
> +++ b/tools/perf/util/arm-spe.c
> @@ -1532,6 +1532,7 @@ static const char * const metadata_per_cpu_fmts[] = {
>   	[ARM_SPE_CPU_MIDR]		= "    MIDR             :0x%"PRIx64"\n",
>   	[ARM_SPE_CPU_PMU_TYPE]		= "    PMU Type         :%"PRId64"\n",
>   	[ARM_SPE_CAP_MIN_IVAL]		= "    Min Interval     :%"PRId64"\n",
> +	[ARM_SPE_CAP_EVENTS]		= "    Events           :0x%"PRIx64"\n",
>   };
>   
>   static void arm_spe_print_info(struct arm_spe *spe, __u64 *arr)
> diff --git a/tools/perf/util/arm-spe.h b/tools/perf/util/arm-spe.h
> index 390679a4af2fb61419bc881b5dc43c01f1dd77d7..a47d3d8fc97e07d1bb41a6776133d0676c335613 100644
> --- a/tools/perf/util/arm-spe.h
> +++ b/tools/perf/util/arm-spe.h
> @@ -47,6 +47,8 @@ enum {
>   	ARM_SPE_CPU_PMU_TYPE,
>   	/* Minimal interval */
>   	ARM_SPE_CAP_MIN_IVAL,
> +	/* Supported events */
> +	ARM_SPE_CAP_EVENTS,
>   	ARM_SPE_CPU_PRIV_MAX,
>   };
>   
>