From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD19BC77B7C for ; Sat, 27 May 2023 13:32:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231387AbjE0Nc5 (ORCPT ); Sat, 27 May 2023 09:32:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59616 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231186AbjE0Nc5 (ORCPT ); Sat, 27 May 2023 09:32:57 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B5A20C3; Sat, 27 May 2023 06:32:55 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 50F7861472; Sat, 27 May 2023 13:32:55 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A7AD8C4339C; Sat, 27 May 2023 13:32:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685194374; bh=2TNQEbJxCXNtnSuWUh8ETIiBTaEmLYOWvno0ZcYi0QU=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=qbzt+NhsrBrEBI2Er2jDNqD8FG0knKYp6WP7OFfJ1+iITD54Vvz7g6MNG4/4Ig5fl qE3X+pVnzPgsBctUKz2quZ3pOoGr+qrS5R3EFZ5jydxqB2g3ES/hfmoJbeM2eYbzWr fmipr3mjLbjWr0J3nB/yBeohPM+35YWkrN0zNo0y3znFpRsH1nDBTzzEsPwnKN2rvR PuarY+iX1O6y+VzZDm6YrS+dIOFCj72wwmp6o+MX2JTgzIiXFgj5Y5FFBnP9+LmnTE ZcujOrKgsDZC22UM6Awr0g5rAgBzoFeDsC8eCl/TpZRjkZPLDoFzEfAqN7QjbfV2w1 tqKh/el+41XQA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1q2u2O-000l67-1p; Sat, 27 May 2023 14:32:52 +0100 Date: Sat, 27 May 2023 14:32:51 +0100 Message-ID: <86jzwtdhmk.wl-maz@kernel.org> From: Marc Zyngier To: Ian Rogers Cc: Oliver Upton , Peter Zijlstra , Ravi Bangoria , Nathan Chancellor , namhyung@kernel.org, eranian@google.com, acme@kernel.org, mark.rutland@arm.com, jolsa@kernel.org, bp@alien8.de, kan.liang@linux.intel.com, adrian.hunter@intel.com, maddy@linux.ibm.com, x86@kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, sandipan.das@amd.com, ananth.narayan@amd.com, santosh.shukla@amd.com, kvmarm@lists.linux.dev Subject: Re: [PATCH v4 3/4] perf/core: Remove pmu linear searching code In-Reply-To: References: <20230504110003.2548-1-ravi.bangoria@amd.com> <20230504110003.2548-4-ravi.bangoria@amd.com> <20230524214133.GA2359762@dev-arch.thelio-3990X> <20230525142031.GU83892@hirez.programming.kicks-ass.net> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: irogers@google.com, oliver.upton@linux.dev, peterz@infradead.org, ravi.bangoria@amd.com, nathan@kernel.org, namhyung@kernel.org, eranian@google.com, acme@kernel.org, mark.rutland@arm.com, jolsa@kernel.org, bp@alien8.de, kan.liang@linux.intel.com, adrian.hunter@intel.com, maddy@linux.ibm.com, x86@kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, sandipan.das@amd.com, ananth.narayan@amd.com, santosh.shukla@amd.com, kvmarm@lists.linux.dev X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-perf-users@vger.kernel.org On Sat, 27 May 2023 00:00:47 +0100, Ian Rogers wrote: >=20 > On Thu, May 25, 2023 at 8:56=E2=80=AFAM Oliver Upton wrote: > > > > On Thu, May 25, 2023 at 04:20:31PM +0200, Peter Zijlstra wrote: > > > On Thu, May 25, 2023 at 07:11:41AM +0000, Oliver Upton wrote: > > > > > > > The PMUv3 driver does pass a name, but it relies on getting back an > > > > allocated pmu id as @type is -1 in the call to perf_pmu_register(). > > > > > > > > What actually broke is how KVM probes for a default core PMU to use= for > > > > a guest. kvm_pmu_probe_armpmu() creates a counter w/ PERF_TYPE_RAW = and > > > > reads the pmu from the returned perf_event. The linear search had t= he > > > > effect of eventually stumbling on the correct core PMU and succeedi= ng. > > > > > > > > Perf folks: is this WAI for heterogenous systems? > > > > > > TBH, I'm not sure. hetero and virt don't mix very well AFAIK and I'm = not > > > sure what ARM64 does here. > > > > > > IIRC the only way is to hard affine things; that is, force vCPU of > > > 'type' to the pCPU mask of 'type' CPUs. > > > > We provide absolutely no illusion of consistency across implementations. > > Userspace can select the PMU type, and then it is a userspace problem > > affining vCPUs to the right pCPUs. > > > > And if they get that wrong, we just bail and refuse to run the vCPU. > > > > > If you don't do that; or let userspace 'override' that, things go > > > sideways *real* fast. > > > > Oh yeah, and I wish PMUs were the only problem with these hetero > > systems... >=20 > Just to add some context from what I understand. There are inbuilt > type numbers for PMUs: > https://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git/tree/inclu= de/uapi/linux/perf_event.h?h=3Dperf-tools-next#n34 > so the PMU generally called /sys/devices/cpu should have type 4 (ARM > give it another name). For heterogeneous ARM there is a single PMU and > the same events are programmed regardless of whether it is a big or a > little core - the cpumask lists all CPUs. I think you misunderstood the way heterogeneous arm64 systems are described . Each CPU type gets its own PMU type, and its own event list. Case in point: $ grep . /sys/devices/*pmu/{type,cpus} /sys/devices/apple_avalanche_pmu/type:9 /sys/devices/apple_blizzard_pmu/type:8 /sys/devices/apple_avalanche_pmu/cpus:4-9 /sys/devices/apple_blizzard_pmu/cpus:0-3 Type 4 (aka PERF_EVENT_RAW) is AFAICT just a way to encode the raw event number, nothing else. Thanks, M. --=20 Without deviation from the norm, progress is not possible.