Re: [PATCH v3 5/6] arm64: dts: renesas: Add R8A78000 X5H DTs

[Marc Zyngier <maz@kernel.org>]

On Tue, 16 Sep 2025 03:38:47 +0100,
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> wrote:
> 
> From: Hai Pham <hai.pham.ud@renesas.com>
> 
> Add initial DT support for R8A78000 (R-Car X5H) SoC.
> 
> [Kuninori: tidyup for upstreaming]
> 
> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
> Signed-off-by: Vinh Nguyen <vinh.nguyen.xz@renesas.com>
> Signed-off-by: Minh Le <minh.le.aj@renesas.com>
> Signed-off-by: Huy Bui <huy.bui.wm@renesas.com>
> Signed-off-by: Khanh Le <khanh.le.xr@renesas.com>
> Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> ---
>  arch/arm64/boot/dts/renesas/r8a78000.dtsi | 756 ++++++++++++++++++++++
>  1 file changed, 756 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/renesas/r8a78000.dtsi
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> new file mode 100644
> index 0000000000000..82e27ce39c127
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi

[...]

> +	soc: soc {
> +		compatible = "simple-bus";
> +		interrupt-parent = <&gic>;
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		prr: chipid@189e0044 {
> +			compatible = "renesas,prr";
> +			reg = <0 0x189e0044 0 4>;
> +		};
> +
> +		/*
> +		 * The ARM GIC-720AE - View 1
> +		 *
> +		 * see
> +		 *	r19uh0244ej0052-r-carx5h.pdf
> +		 *	- attachments: 002_R-CarX5H_Address_Map_r0p51.xlsx
> +		 *	 - sheet [RT]
> +		 *	  - line 619

Are these documents publicly available? If not, I don't think this
helps much.

> +		 */
> +		gic: interrupt-controller@39000000 {
> +			compatible = "arm,gic-v3";
> +			#interrupt-cells = <3>;
> +			#address-cells = <0>;
> +			interrupt-controller;
> +			reg = <0 0x39000000 0 0x20000>, // GICD
> +			      <0 0x39080000 0 0x40000>; // GICR

In v2, you indicated that your GIC was configured for GICv4.1, which
implied 256kB frames for each redistributor. Here, you have either
just enough space for 32 RDs for a GICv3, or 16 RDs for GICv4.

So either this is wrong, and you're missing half of the RD space, or
v2 was wrong. Which one is it?

> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

No ITS? That seems... surprising.

> +		};

[...]

> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> +				      <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> +				      <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> +				      <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
> +				      <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
> +		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
> +				  "hyp-virt";
> +	};

Why use interrupts-extended here? Everywhere else, you're using the
basic interrupt specifier. Can't you move the interrupt-parent
property to the top and simplify the timer (and everything else
outside of the 'soc' node?

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.