From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33DCCC8E7; Mon, 4 Dec 2023 08:22:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gLvzMSTe" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A425BC433C7; Mon, 4 Dec 2023 08:22:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1701678148; bh=d5xd1DNNe8JHTchZ1N0VUvsvu4Wgsp0ilZmuF8NZBgQ=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=gLvzMSTejitY38rVbVjqGTXEH+MOT+PcFUG93c0YgGr336/kcmHuZtMyWAJUur9dj ylPSMIrRC6wrFF6JH8llfP4lnxofw9JWIRKnnRbtGCKoUGUmv+BvE3zqzIXchLcyIJ mN17ecVhBQKZ+dWBJT03lM6eIzrvq3+6DCrCLjqF0YaafhQ/cwUi5brHnGaFs86F8I 4b4iOCkO3HIr/O4KlY6DcVzLuCyIZfchlvHG3+jOPQHbJfDpNjrPmWxRBahk/mvnEW MFOGWM7jIeEf4pzDdJPtfQVNnDvtINBdxCPnCpYJn/bidcPDKIQxzXDyMbQL9ojseN 70ErEzj5WRZbw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1rA4Di-0018lj-9m; Mon, 04 Dec 2023 08:22:26 +0000 Date: Mon, 04 Dec 2023 08:22:25 +0000 Message-ID: <86v89ebcn2.wl-maz@kernel.org> From: Marc Zyngier To: Anshuman Khandual Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, will@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, Mark Brown , James Clark , Rob Herring , Suzuki Poulose , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , linux-perf-users@vger.kernel.org, Oliver Upton , James Morse , kvmarm@lists.linux.dev Subject: Re: [PATCH V15 2/8] KVM: arm64: Prevent guest accesses into BRBE system registers/instructions In-Reply-To: <20231201053906.1261704-3-anshuman.khandual@arm.com> References: <20231201053906.1261704-1-anshuman.khandual@arm.com> <20231201053906.1261704-3-anshuman.khandual@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: anshuman.khandual@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, will@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, broonie@kernel.org, james.clark@arm.com, robh@kernel.org, suzuki.poulose@arm.com, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, oliver.upton@linux.dev, james.morse@arm.com, kvmarm@lists.linux.dev X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Fri, 01 Dec 2023 05:39:00 +0000, Anshuman Khandual wrote: > > Currently BRBE feature is not supported in a guest environment. This hides > BRBE feature availability via masking ID_AA64DFR0_EL1.BRBE field. This also > blocks guest accesses into BRBE system registers and instructions as if the > underlying hardware never implemented FEAT_BRBE feature. > > Cc: Marc Zyngier > Cc: Oliver Upton > Cc: James Morse > Cc: Suzuki K Poulose > Cc: Catalin Marinas > Cc: Will Deacon > Cc: kvmarm@lists.linux.dev > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Signed-off-by: Anshuman Khandual > --- > arch/arm64/kvm/sys_regs.c | 130 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 130 insertions(+) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 4735e1b37fb3..42701065b3cd 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -1583,6 +1583,9 @@ static u64 read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, > /* Hide SPE from guests */ > val &= ~ID_AA64DFR0_EL1_PMSVer_MASK; > > + /* Hide BRBE from guests */ > + val &= ~ID_AA64DFR0_EL1_BRBE_MASK; > + > return val; > } > > @@ -2042,6 +2045,8 @@ static const struct sys_reg_desc sys_reg_descs[] = { > { SYS_DESC(SYS_DC_CISW), access_dcsw }, > { SYS_DESC(SYS_DC_CIGSW), access_dcgsw }, > { SYS_DESC(SYS_DC_CIGDSW), access_dcgsw }, > + { SYS_DESC(OP_BRB_IALL), undef_access }, > + { SYS_DESC(OP_BRB_INJ), undef_access }, > > DBG_BCR_BVR_WCR_WVR_EL1(0), > DBG_BCR_BVR_WCR_WVR_EL1(1), > @@ -2072,6 +2077,131 @@ static const struct sys_reg_desc sys_reg_descs[] = { > { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, > { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, > > + /* > + * BRBE branch record sysreg address space is interleaved between > + * corresponding BRBINF_EL1, BRBSRC_EL1, and BRBTGT_EL1. > + */ > + { SYS_DESC(SYS_BRBINF0_EL1), undef_access }, > + { SYS_DESC(SYS_BRBSRC0_EL1), undef_access }, > + { SYS_DESC(SYS_BRBTGT0_EL1), undef_access }, > + { SYS_DESC(SYS_BRBINF16_EL1), undef_access }, > + { SYS_DESC(SYS_BRBSRC16_EL1), undef_access }, > + { SYS_DESC(SYS_BRBTGT16_EL1), undef_access }, Surely we can do better than this wall of text. Please look at what we do for the debug registers, and adopt a similar pattern. This should result in one line per group of 3 registers. What is the plan for KVM support beyond this? M. -- Without deviation from the norm, progress is not possible.