From: Marc Zyngier <maz@kernel.org>
To: Colton Lewis <coltonlewis@google.com>
Cc: kvm@vger.kernel.org, pbonzini@redhat.com, corbet@lwn.net,
linux@armlinux.org.uk, catalin.marinas@arm.com, will@kernel.org,
oliver.upton@linux.dev, mizhang@google.com, joey.gouly@arm.com,
suzuki.poulose@arm.com, yuzenghui@huawei.com,
mark.rutland@arm.com, shuah@kernel.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
linux-perf-users@vger.kernel.org,
linux-kselftest@vger.kernel.org
Subject: Re: [PATCH v3 10/22] KVM: arm64: Set up FGT for Partitioned PMU
Date: Sat, 28 Jun 2025 09:25:35 +0100 [thread overview]
Message-ID: <871pr4ff28.wl-maz@kernel.org> (raw)
In-Reply-To: <gsntbjq89am2.fsf@coltonlewis-kvm.c.googlers.com>
On Fri, 27 Jun 2025 21:45:57 +0100,
Colton Lewis <coltonlewis@google.com> wrote:
>
> Marc Zyngier <maz@kernel.org> writes:
>
> > On Thu, 26 Jun 2025 21:04:46 +0100,
> > Colton Lewis <coltonlewis@google.com> wrote:
>
> >> +static inline void __activate_pmu_fgt(struct kvm_vcpu *vcpu)
> >> +{
> >> + struct kvm_cpu_context *hctxt = host_data_ptr(host_ctxt);
> >> + struct kvm *kvm = kern_hyp_va(vcpu->kvm);
> >> + u64 set;
> >> + u64 clr;
> >> +
> >> + set = HDFGRTR_EL2_PMOVS
> >> + | HDFGRTR_EL2_PMCCFILTR_EL0
> >> + | HDFGRTR_EL2_PMEVTYPERn_EL0;
> >> + clr = HDFGRTR_EL2_PMUSERENR_EL0
> >> + | HDFGRTR_EL2_PMSELR_EL0
> >> + | HDFGRTR_EL2_PMINTEN
> >> + | HDFGRTR_EL2_PMCNTEN
> >> + | HDFGRTR_EL2_PMCCNTR_EL0
> >> + | HDFGRTR_EL2_PMEVCNTRn_EL0;
> >> +
> >> + update_fgt_traps_cs(hctxt, vcpu, kvm, HDFGRTR_EL2, clr, set);
> >> +
> >> + set = HDFGWTR_EL2_PMOVS
> >> + | HDFGWTR_EL2_PMCCFILTR_EL0
> >> + | HDFGWTR_EL2_PMEVTYPERn_EL0;
> >> + clr = HDFGWTR_EL2_PMUSERENR_EL0
> >> + | HDFGWTR_EL2_PMCR_EL0
> >> + | HDFGWTR_EL2_PMSELR_EL0
> >> + | HDFGWTR_EL2_PMINTEN
> >> + | HDFGWTR_EL2_PMCNTEN
> >> + | HDFGWTR_EL2_PMCCNTR_EL0
> >> + | HDFGWTR_EL2_PMEVCNTRn_EL0;
> >> +
> >> + update_fgt_traps_cs(hctxt, vcpu, kvm, HDFGWTR_EL2, clr, set);
> >> +
> >> + if (!cpus_have_final_cap(ARM64_HAS_FGT2))
> >> + return;
> >> +
> >> + set = HDFGRTR2_EL2_nPMICFILTR_EL0
> >> + | HDFGRTR2_EL2_nPMICNTR_EL0;
> >> + clr = 0;
> >> +
> >> + update_fgt_traps_cs(hctxt, vcpu, kvm, HDFGRTR2_EL2, clr, set);
> >> +
> >> + set = HDFGWTR2_EL2_nPMICFILTR_EL0
> >> + | HDFGWTR2_EL2_nPMICNTR_EL0;
> >> + clr = 0;
> >> +
> >> + update_fgt_traps_cs(hctxt, vcpu, kvm, HDFGWTR2_EL2, clr, set);
>
> > This feels wrong. There should be one place to populate the FGTs that
> > apply to a guest as set from the host, not two or more.
>
> > There is such a construct in the SME series, and maybe you could have
> > a look at it, specially if the trap configuration is this static.
>
> > M.
>
> > --
> > Without deviation from the norm, progress is not possible.
>
> I'm assuming you are referring to Mark Brown's series [1], specifically
> patches 5 and 18 and I see what you mean.
>
> You are probably thinking configuration should happen from
> sys_regs.c:kvm_calculate_traps or thereabout and should be setting bits
> in the existing kvm->arch.fgt array.
>
> Correct me if I'm mistaken.
I'm saying there should be exactly one place where we write to the
individual trap registers, and that the source of these settings
should be equally unique when they are immutable in the lifetime of
the guest.
That's the existing pattern for most trap configuration, including
HCR_EL2, ICH_HCR_EL2, HCRX_EL2, and the FGU configuration that
trickles into the actual trap registers, and I want to stick with it
if at all possible.
The way it is done in the SME series may be reasonable, but I haven't
reviewed this series at all. I'm merely pointing out that similar
constructs exist for other features.
M.
--
Jazz isn't dead. It just smells funny.
next prev parent reply other threads:[~2025-06-28 8:25 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-26 20:04 [PATCH v3 00/22] ARM64 PMU Partitioning Colton Lewis
2025-06-26 20:04 ` [PATCH v3 01/22] arm64: cpufeature: Add cpucap for HPMN0 Colton Lewis
2025-07-07 16:05 ` Mark Rutland
2025-07-08 22:34 ` Colton Lewis
2025-06-26 20:04 ` [PATCH v3 02/22] arm64: Generate sign macro for sysreg Enums Colton Lewis
2025-06-27 9:04 ` Ben Horgan
2025-06-27 20:45 ` Colton Lewis
2025-06-27 20:55 ` Oliver Upton
2025-06-30 17:42 ` Colton Lewis
2025-06-27 13:23 ` Marc Zyngier
2025-07-07 16:07 ` Mark Rutland
2025-06-26 20:04 ` [PATCH v3 03/22] KVM: arm64: Define PMI{CNTR,FILTR}_EL0 as undef_access Colton Lewis
2025-06-27 13:31 ` Marc Zyngier
2025-06-27 20:45 ` Colton Lewis
2025-06-26 20:04 ` [PATCH v3 04/22] KVM: arm64: Cleanup PMU includes Colton Lewis
2025-07-07 16:13 ` Mark Rutland
2025-07-08 22:37 ` Colton Lewis
2025-06-26 20:04 ` [PATCH v3 05/22] KVM: arm64: Reorganize PMU functions Colton Lewis
2025-06-26 20:04 ` [PATCH v3 06/22] perf: arm_pmuv3: Introduce method to partition the PMU Colton Lewis
2025-07-07 16:57 ` Mark Rutland
2025-07-07 19:07 ` Oliver Upton
2025-07-08 22:38 ` Colton Lewis
2025-07-08 22:41 ` Oliver Upton
2025-06-26 20:04 ` [PATCH v3 07/22] perf: arm_pmuv3: Generalize counter bitmasks Colton Lewis
2025-07-07 16:58 ` Mark Rutland
2025-07-08 22:38 ` Colton Lewis
2025-06-26 20:04 ` [PATCH v3 08/22] perf: arm_pmuv3: Keep out of guest counter partition Colton Lewis
2025-06-26 20:04 ` [PATCH v3 09/22] KVM: arm64: Correct kvm_arm_pmu_get_max_counters() Colton Lewis
2025-06-27 13:36 ` Marc Zyngier
2025-06-30 17:42 ` Colton Lewis
2025-06-26 20:04 ` [PATCH v3 10/22] KVM: arm64: Set up FGT for Partitioned PMU Colton Lewis
2025-06-27 15:01 ` Marc Zyngier
2025-06-27 20:45 ` Colton Lewis
2025-06-28 8:25 ` Marc Zyngier [this message]
2025-06-26 20:04 ` [PATCH v3 11/22] KVM: arm64: Writethrough trapped PMEVTYPER register Colton Lewis
2025-06-26 20:04 ` [PATCH v3 12/22] KVM: arm64: Use physical PMSELR for PMXEVTYPER if partitioned Colton Lewis
2025-06-26 20:04 ` [PATCH v3 13/22] KVM: arm64: Writethrough trapped PMOVS register Colton Lewis
2025-06-26 20:04 ` [PATCH v3 14/22] KVM: arm64: Write fast path PMU register handlers Colton Lewis
2025-06-26 20:04 ` [PATCH v3 15/22] KVM: arm64: Setup MDCR_EL2 to handle a partitioned PMU Colton Lewis
2025-06-26 20:04 ` [PATCH v3 16/22] KVM: arm64: Account for partitioning in PMCR_EL0 access Colton Lewis
2025-06-26 20:04 ` [PATCH v3 17/22] KVM: arm64: Context swap Partitioned PMU guest registers Colton Lewis
2025-06-26 20:04 ` [PATCH v3 18/22] KVM: arm64: Enforce PMU event filter at vcpu_load() Colton Lewis
2025-06-26 20:04 ` [PATCH v3 19/22] perf: arm_pmuv3: Handle IRQs for Partitioned PMU guest counters Colton Lewis
2025-06-26 20:04 ` [PATCH v3 20/22] KVM: arm64: Inject recorded guest interrupts Colton Lewis
2025-06-26 20:04 ` [PATCH v3 21/22] KVM: arm64: Add ioctl to partition the PMU when supported Colton Lewis
2025-06-26 20:04 ` [PATCH v3 22/22] KVM: arm64: selftests: Add test case for partitioned PMU Colton Lewis
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