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smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=SE49GUQb; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=hwPVCOob; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="SE49GUQb"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="hwPVCOob" From: Thomas Gleixner DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1707818693; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=Y1HrfL+SrlW2XWR5pU7cGgxYMFs+Qr2zZ76ZBVxutfE=; b=SE49GUQbwTclIrg8Ek0Z3VpThQD1o9FAH8SAfIXoKnzTV3UsTWw9PR3oootZv4e+BrIiEw mdQccGiNG42+Pm2ePTR4i97kp8932eaGmbf9YEyCPmZhmlW6DTxYRik/XdRPpaf/1d9Rj+ iw237txMkf2vF9jD/1ZLzDd0rm8LrsgK/C2xIiSWgoOKHIUVHZ9nngnvzOVUFKnc6moxK7 BpEj8jkWpHHDobcUxfUsyG+G/u9okIlxlJR4RBySpQ43POtEj6N7+cSAuQiP7GiM5XpWMC zt2UBKcuYOqCl9/NGww8Fi+s6sVfQA4TLjGzQeVeq9V65GziT/r7Yaga1vZYqA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1707818693; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=Y1HrfL+SrlW2XWR5pU7cGgxYMFs+Qr2zZ76ZBVxutfE=; b=hwPVCOobELnpGmo9aIjJ/oKtSoM7jE5zNUcYVknaR65ECFvfFEULvht2Ghlz1V5bazoRzP gBUt4M68cX7NwTDg== To: Yu Chien Peter Lin , acme@kernel.org, adrian.hunter@intel.com, ajones@ventanamicro.com, alexander.shishkin@linux.intel.com, andre.przywara@arm.com, anup@brainfault.org, aou@eecs.berkeley.edu, atishp@atishpatra.org, conor+dt@kernel.org, conor.dooley@microchip.com, conor@kernel.org, devicetree@vger.kernel.org, evan@rivosinc.com, geert+renesas@glider.be, guoren@kernel.org, heiko@sntech.de, irogers@google.com, jernej.skrabec@gmail.com, jolsa@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-sunxi@lists.linux.dev, locus84@andestech.com, magnus.damm@gmail.com, mark.rutland@arm.com, mingo@redhat.com, n.shubin@yadro.com, namhyung@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, peterlin@andestech.com, peterz@infradead.org, prabhakar.mahadev-lad.rj@bp.renesas.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, sunilvl@ventanamicro.com, tim609@andestech.com, uwu@icenowy.me, wens@csie.org, will@kernel.org, inochiama@outlook.com, unicorn_wang@outlook.com, wefu@redhat.com Cc: Randolph , Atish Patra Subject: Re: [PATCH v8 02/10] irqchip/riscv-intc: Allow large non-standard interrupt number In-Reply-To: <20240129092553.2058043-3-peterlin@andestech.com> References: <20240129092553.2058043-1-peterlin@andestech.com> <20240129092553.2058043-3-peterlin@andestech.com> Date: Tue, 13 Feb 2024 11:04:53 +0100 Message-ID: <877cj8issa.ffs@tglx> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Mon, Jan 29 2024 at 17:25, Yu Chien Peter Lin wrote: > static asmlinkage void riscv_intc_irq(struct pt_regs *regs) > { > unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; > > - if (unlikely(cause >= BITS_PER_LONG)) > - panic("unexpected interrupt cause"); > - > - generic_handle_domain_irq(intc_domain, cause); > + if (generic_handle_domain_irq(intc_domain, cause)) > + pr_warn_ratelimited("Failed to handle interrupt (cause: %ld)\n", > + cause); Either let the cause stick out or you need brackets. See: https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#bracket-rules > } > > /* > @@ -93,6 +95,14 @@ static int riscv_intc_domain_alloc(struct irq_domain *domain, > if (ret) > return ret; > > + /* > + * Only allow hwirq for which we have corresponding standard or > + * custom interrupt enable register. > + */ > + if ((riscv_intc_nr_irqs <= hwirq && hwirq < riscv_intc_custom_base) || > + (riscv_intc_custom_base + riscv_intc_custom_nr_irqs) <= hwirq) > + return -EINVAL; Duh. This mix of ordering required to read this 3 times. What's wrong with writing this consistently: if ((hwirq >= riscv_intc_nr_irqs && hwirq < riscv_intc_custom_base) || (hwirq >= iscv_intc_custom_base + riscv_intc_custom_nr_irqs) return -EINVAL; Hmm? > - pr_info("%d local interrupts mapped\n", BITS_PER_LONG); > + pr_info("%d local interrupts mapped\n", riscv_intc_nr_irqs); > + if (riscv_intc_custom_nr_irqs) > + pr_info("%d custom local interrupts mapped\n", > + riscv_intc_custom_nr_irqs); See bracket rules. > return 0; > } > @@ -166,6 +178,10 @@ static int __init riscv_intc_init(struct device_node *node, > return 0; > } > > + riscv_intc_nr_irqs = BITS_PER_LONG; > + riscv_intc_custom_base = riscv_intc_nr_irqs; Why don't you initialize the static variables with constants right away? > + riscv_intc_custom_nr_irqs = 0; It's already 0, no? > return riscv_intc_init_common(of_node_to_fwnode(node)); > } Thanks, tglx