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X-CSE-ConnectionGUID: QIzIKBJTRh+hOM+HKg/nUQ== X-CSE-MsgGUID: 2kUr60r2Qdm6yJhOl8Hcug== X-IronPort-AV: E=McAfee;i="6700,10204,11190"; a="24537564" X-IronPort-AV: E=Sophos;i="6.10,216,1719903600"; d="scan'208";a="24537564" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2024 22:00:57 -0700 X-CSE-ConnectionGUID: /0gdkZzaSgSw8Ch+aG9fPg== X-CSE-MsgGUID: sqkvnjgxR6+Kj6hU1mGZMA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,216,1719903600"; d="scan'208";a="66853609" Received: from unknown (HELO [10.238.2.208]) ([10.238.2.208]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2024 22:00:52 -0700 Message-ID: <8843b93e-72e1-445a-b7ad-c9f186e77f16@linux.intel.com> Date: Tue, 10 Sep 2024 13:00:49 +0800 Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v3 15/58] perf/x86: Support switch_interrupt interface To: Colton Lewis , Mingwei Zhang Cc: seanjc@google.com, pbonzini@redhat.com, xiong.y.zhang@intel.com, kan.liang@intel.com, zhenyuw@linux.intel.com, manali.shukla@amd.com, sandipan.das@amd.com, jmattson@google.com, eranian@google.com, irogers@google.com, namhyung@kernel.org, gce-passthrou-pmu-dev@google.com, samantha.alt@intel.com, zhiyuan.lv@intel.com, yanfei.xu@intel.com, like.xu.linux@gmail.com, peterz@infradead.org, rananta@google.com, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org References: Content-Language: en-US From: "Mi, Dapeng" In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 9/10/2024 6:11 AM, Colton Lewis wrote: > Mingwei Zhang writes: > >> From: Kan Liang >> Implement switch_interrupt interface for x86 PMU, switch PMI to dedicated >> KVM_GUEST_PMI_VECTOR at perf guest enter, and switch PMI back to >> NMI at perf guest exit. >> Signed-off-by: Xiong Zhang >> Signed-off-by: Kan Liang >> Tested-by: Yongwei Ma >> Signed-off-by: Mingwei Zhang >> --- >> arch/x86/events/core.c | 11 +++++++++++ >> 1 file changed, 11 insertions(+) >> diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c >> index 5bf78cd619bf..b17ef8b6c1a6 100644 >> --- a/arch/x86/events/core.c >> +++ b/arch/x86/events/core.c >> @@ -2673,6 +2673,15 @@ static bool x86_pmu_filter(struct pmu *pmu, int >> cpu) >> return ret; >> } >> +static void x86_pmu_switch_interrupt(bool enter, u32 guest_lvtpc) >> +{ >> + if (enter) >> + apic_write(APIC_LVTPC, APIC_DM_FIXED | KVM_GUEST_PMI_VECTOR | >> + (guest_lvtpc & APIC_LVT_MASKED)); >> + else >> + apic_write(APIC_LVTPC, APIC_DM_NMI); >> +} >> + > Similar issue I point out in an earlier patch. #define > KVM_GUEST_PMI_VECTOR is guarded by CONFIG_KVM but this code is not, > which can result in compile errors. Yes, thanks for pointing this. > >> static struct pmu pmu = { >> .pmu_enable = x86_pmu_enable, >> .pmu_disable = x86_pmu_disable, >> @@ -2702,6 +2711,8 @@ static struct pmu pmu = { >> .aux_output_match = x86_pmu_aux_output_match, >> .filter = x86_pmu_filter, >> + >> + .switch_interrupt = x86_pmu_switch_interrupt, >> }; >> void arch_perf_update_userpage(struct perf_event *event,