* [PATCH v2 0/4] perf vendor events riscv: Add XuanTie C930 JSON files
@ 2025-11-21 6:34 cp0613
2025-11-21 6:34 ` [PATCH v2 1/4] dt-bindings: vendor-prefixes: Add prefix for XuanTie cp0613
` (3 more replies)
0 siblings, 4 replies; 13+ messages in thread
From: cp0613 @ 2025-11-21 6:34 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, pjw, palmer, aou, peterz, mingo, acme,
namhyung, mark.rutland, alexander.shishkin, jolsa, irogers,
adrian.hunter, james.clark, guoren
Cc: devicetree, linux-perf-users, linux-riscv, linux-kernel, Chen Pei
From: Chen Pei <cp0613@linux.alibaba.com>
XuanTie[1] is the RISC-V processor brand of C-SKY Microsystems Co., Ltd.
This patch series first adds vendor XuanTie, then adds XuanTie C930 CPU
compatible, and finally adds pmu json files for XuanTie C930, including
topdown and some other metric groups.
Note:
According to the "Standard Manufacturer's IDENTIFICATION CODE"[2], the
manufacturer of Code '0x5b7' has changed to C-SKY Microsystems Co., Ltd.
[1] https://www.xrvm.com/
[2] https://www.jedec.org/standards-documents/docs/jep-106ab
Chen Pei (4):
dt-bindings: vendor-prefixes: Add prefix for XuanTie
dt-bindings: riscv: Add XuanTie C930 CPU compatible
perf vendor events riscv: Add XuanTie C930 JSON file
perf vendor events riscv: Add XuanTie C930 metrics
.../devicetree/bindings/riscv/cpus.yaml | 1 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 +
.../arch/riscv/xuantie/c930/basic.json | 117 ++++
.../arch/riscv/xuantie/c930/ieu.json | 97 ++++
.../arch/riscv/xuantie/c930/ifu.json | 62 ++
.../arch/riscv/xuantie/c930/l2c.json | 87 +++
.../arch/riscv/xuantie/c930/lsu.json | 182 ++++++
.../arch/riscv/xuantie/c930/metrics.json | 538 ++++++++++++++++++
.../arch/riscv/xuantie/c930/vfpu.json | 177 ++++++
10 files changed, 1264 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/riscv/xuantie/c930/basic.json
create mode 100644 tools/perf/pmu-events/arch/riscv/xuantie/c930/ieu.json
create mode 100644 tools/perf/pmu-events/arch/riscv/xuantie/c930/ifu.json
create mode 100644 tools/perf/pmu-events/arch/riscv/xuantie/c930/l2c.json
create mode 100644 tools/perf/pmu-events/arch/riscv/xuantie/c930/lsu.json
create mode 100644 tools/perf/pmu-events/arch/riscv/xuantie/c930/metrics.json
create mode 100644 tools/perf/pmu-events/arch/riscv/xuantie/c930/vfpu.json
--
2.50.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 1/4] dt-bindings: vendor-prefixes: Add prefix for XuanTie
2025-11-21 6:34 [PATCH v2 0/4] perf vendor events riscv: Add XuanTie C930 JSON files cp0613
@ 2025-11-21 6:34 ` cp0613
2025-11-21 8:22 ` Guo Ren
2025-11-21 9:01 ` Krzysztof Kozlowski
2025-11-21 6:34 ` [PATCH v2 2/4] dt-bindings: riscv: Add XuanTie C930 CPU compatible cp0613
` (2 subsequent siblings)
3 siblings, 2 replies; 13+ messages in thread
From: cp0613 @ 2025-11-21 6:34 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, pjw, palmer, aou, peterz, mingo, acme,
namhyung, mark.rutland, alexander.shishkin, jolsa, irogers,
adrian.hunter, james.clark, guoren
Cc: devicetree, linux-perf-users, linux-riscv, linux-kernel, Chen Pei
From: Chen Pei <cp0613@linux.alibaba.com>
Add new vendor strings to dt bindings for RISC-V vendor XuanTie.
Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index f1d1882009ba..5d28b2da94cd 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1829,6 +1829,8 @@ patternProperties:
description: Xilinx
"^xnano,.*":
description: Xnano
+ "^xuantie,.*":
+ description: C-SKY Microsystems Co., Ltd. (XuanTie)
"^xunlong,.*":
description: Shenzhen Xunlong Software CO.,Limited
"^xylon,.*":
--
2.50.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 2/4] dt-bindings: riscv: Add XuanTie C930 CPU compatible
2025-11-21 6:34 [PATCH v2 0/4] perf vendor events riscv: Add XuanTie C930 JSON files cp0613
2025-11-21 6:34 ` [PATCH v2 1/4] dt-bindings: vendor-prefixes: Add prefix for XuanTie cp0613
@ 2025-11-21 6:34 ` cp0613
2025-11-21 8:23 ` Guo Ren
2025-11-21 9:01 ` Krzysztof Kozlowski
2025-11-21 6:34 ` [PATCH v2 3/4] perf vendor events riscv: Add XuanTie C930 JSON file cp0613
2025-11-21 6:34 ` [PATCH v2 4/4] perf vendor events riscv: Add XuanTie C930 metrics cp0613
3 siblings, 2 replies; 13+ messages in thread
From: cp0613 @ 2025-11-21 6:34 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, pjw, palmer, aou, peterz, mingo, acme,
namhyung, mark.rutland, alexander.shishkin, jolsa, irogers,
adrian.hunter, james.clark, guoren
Cc: devicetree, linux-perf-users, linux-riscv, linux-kernel, Chen Pei
From: Chen Pei <cp0613@linux.alibaba.com>
Update Documentation for supporting XuanTie C930.
Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 153d0dac57fb..581a95eba932 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -65,6 +65,7 @@ properties:
- thead,c908
- thead,c910
- thead,c920
+ - xuantie,c930
- const: riscv
- items:
- enum:
--
2.50.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 3/4] perf vendor events riscv: Add XuanTie C930 JSON file
2025-11-21 6:34 [PATCH v2 0/4] perf vendor events riscv: Add XuanTie C930 JSON files cp0613
2025-11-21 6:34 ` [PATCH v2 1/4] dt-bindings: vendor-prefixes: Add prefix for XuanTie cp0613
2025-11-21 6:34 ` [PATCH v2 2/4] dt-bindings: riscv: Add XuanTie C930 CPU compatible cp0613
@ 2025-11-21 6:34 ` cp0613
2025-11-21 6:34 ` [PATCH v2 4/4] perf vendor events riscv: Add XuanTie C930 metrics cp0613
3 siblings, 0 replies; 13+ messages in thread
From: cp0613 @ 2025-11-21 6:34 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, pjw, palmer, aou, peterz, mingo, acme,
namhyung, mark.rutland, alexander.shishkin, jolsa, irogers,
adrian.hunter, james.clark, guoren
Cc: devicetree, linux-perf-users, linux-riscv, linux-kernel, Chen Pei
From: Chen Pei <cp0613@linux.alibaba.com>
Add pmu json file of XuanTie C930.
Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
---
tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 +
.../arch/riscv/xuantie/c930/basic.json | 117 +++++++++++
.../arch/riscv/xuantie/c930/ieu.json | 97 ++++++++++
.../arch/riscv/xuantie/c930/ifu.json | 62 ++++++
.../arch/riscv/xuantie/c930/l2c.json | 87 +++++++++
.../arch/riscv/xuantie/c930/lsu.json | 182 ++++++++++++++++++
.../arch/riscv/xuantie/c930/vfpu.json | 177 +++++++++++++++++
7 files changed, 723 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/riscv/xuantie/c930/basic.json
create mode 100644 tools/perf/pmu-events/arch/riscv/xuantie/c930/ieu.json
create mode 100644 tools/perf/pmu-events/arch/riscv/xuantie/c930/ifu.json
create mode 100644 tools/perf/pmu-events/arch/riscv/xuantie/c930/l2c.json
create mode 100644 tools/perf/pmu-events/arch/riscv/xuantie/c930/lsu.json
create mode 100644 tools/perf/pmu-events/arch/riscv/xuantie/c930/vfpu.json
diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv
index 0a7e7dcc81be..0cac854f1738 100644
--- a/tools/perf/pmu-events/arch/riscv/mapfile.csv
+++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
@@ -20,5 +20,6 @@
0x489-0x8000000000000008-0x[[:xdigit:]]+,v1,sifive/p550,core
0x489-0x8000000000000[1-6]08-0x[9b][[:xdigit:]]+,v1,sifive/p650,core
0x5b7-0x0-0x0,v1,thead/c900-legacy,core
+0x5b7-0x8000000009201600-0x[[:xdigit:]]+,v1,xuantie/c930,core
0x67e-0x80000000db0000[89]0-0x[[:xdigit:]]+,v1,starfive/dubhe-80,core
0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core
diff --git a/tools/perf/pmu-events/arch/riscv/xuantie/c930/basic.json b/tools/perf/pmu-events/arch/riscv/xuantie/c930/basic.json
new file mode 100644
index 000000000000..afb4bec67af9
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/xuantie/c930/basic.json
@@ -0,0 +1,117 @@
+[
+ {
+ "EventName": "cycles.hart",
+ "EventCode": "0x00000001",
+ "BriefDescription": "cpu execute cycle"
+ },
+ {
+ "EventName": "inst.ret",
+ "EventCode": "0x00000002",
+ "BriefDescription": "inst retire num"
+ },
+ {
+ "EventName": "inst.brjmp.spec",
+ "EventCode": "0x00000003",
+ "BriefDescription": "speculative execute br num"
+ },
+ {
+ "EventName": "inst.mispred.brjmp.spec",
+ "EventCode": "0x00000004",
+ "BriefDescription": "speculative execute br mispred num"
+ },
+ {
+ "EventName": "cache.l1i.rd.access",
+ "EventCode": "0x00000005",
+ "BriefDescription": "l1 icache acc num"
+ },
+ {
+ "EventName": "cache.l1i.rd.miss",
+ "EventCode": "0x00000006",
+ "BriefDescription": "l1 icache acc miss num"
+ },
+ {
+ "EventName": "cache.l1d.rd.access",
+ "EventCode": "0x00000007",
+ "BriefDescription": "l1 dcache load acc num"
+ },
+ {
+ "EventName": "cache.l1d.rd.miss",
+ "EventCode": "0x00000008",
+ "BriefDescription": "l1 dcache load acc miss num"
+ },
+ {
+ "EventName": "tlb.l1i.access",
+ "EventCode": "0x00000009",
+ "BriefDescription": "itlb acc num"
+ },
+ {
+ "EventName": "tlb.l1i.miss",
+ "EventCode": "0x0000000a",
+ "BriefDescription": "itlb acc miss num"
+ },
+ {
+ "EventName": "tlb.l1d.access",
+ "EventCode": "0x0000000b",
+ "BriefDescription": "dtlb acc num"
+ },
+ {
+ "EventName": "tlb.l1d.miss",
+ "EventCode": "0x0000000c",
+ "BriefDescription": "dtlb acc miss num"
+ },
+ {
+ "EventName": "tlb.pf.access",
+ "EventCode": "0x0000000d",
+ "BriefDescription": "ptlb acc num"
+ },
+ {
+ "EventName": "tlb.pf.miss",
+ "EventCode": "0x0000000e",
+ "BriefDescription": "ptlb acc miss num"
+ },
+ {
+ "EventName": "cache.l2.access",
+ "EventCode": "0x0000000f",
+ "BriefDescription": "l2 acc num"
+ },
+ {
+ "EventName": "cache.l2.miss",
+ "EventCode": "0x00000010",
+ "BriefDescription": "l2 acc miss num"
+ },
+ {
+ "EventName": "uop.spec",
+ "EventCode": "0x00000011",
+ "BriefDescription": "rename stage issue slots num"
+ },
+ {
+ "EventName": "topdown.frontend_bound.slots",
+ "EventCode": "0x00000012",
+ "BriefDescription": "rename stage no stall and no in recovery, rename stage bubble slot num"
+ },
+ {
+ "EventName": "topdown.bad_speculation.recovery_bubbles",
+ "EventCode": "0x00000013",
+ "BriefDescription": "backend flush, rename stage stall cycle num"
+ },
+ {
+ "EventName": "topdown.frontend_bound.latency.slots",
+ "EventCode": "0x00000014",
+ "BriefDescription": "rename stage no stall, frontend waste slots num"
+ },
+ {
+ "EventName": "topdown.backend_bound.memory.load",
+ "EventCode": "0x00000015",
+ "BriefDescription": "issue queue full, and exist inflight load cycle num"
+ },
+ {
+ "EventName": "topdown.backend_bound.memory.store",
+ "EventCode": "0x00000016",
+ "BriefDescription": "issue queue full, and exist inflight store cycle num"
+ },
+ {
+ "EventName": "uop.ret",
+ "EventCode": "0x00000017",
+ "BriefDescription": "retire uop num"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/xuantie/c930/ieu.json b/tools/perf/pmu-events/arch/riscv/xuantie/c930/ieu.json
new file mode 100644
index 000000000000..61e57c0e415b
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/xuantie/c930/ieu.json
@@ -0,0 +1,97 @@
+[
+ {
+ "EventName": "topdown.backend_bound.core.barrier_csr",
+ "EventCode": "0x0000003c",
+ "BriefDescription": "Stall cycles caused by CSR barrier at Rename"
+ },
+ {
+ "EventName": "topdown.backend_bound.core.highload",
+ "EventCode": "0x0000003d",
+ "BriefDescription": "Stall cycles caused by high load (ptag full, etc.) at Rename"
+ },
+ {
+ "EventName": "topdown.backend_bound.core.rob_full",
+ "EventCode": "0x0000003e",
+ "BriefDescription": "Stall cycles caused by ROB full at Rename"
+ },
+ {
+ "EventName": "topdown.backend_bound.core.flush_or_rebuild",
+ "EventCode": "0x0000003f",
+ "BriefDescription": "Stall cycles caused by flush or unfinished rebuilding at Rename"
+ },
+ {
+ "EventName": "ieu.de.inst_cnt",
+ "EventCode": "0x00000040",
+ "BriefDescription": "instr nums in de"
+ },
+ {
+ "EventName": "ieu.rn.inst_cnt",
+ "EventCode": "0x00000041",
+ "BriefDescription": "instr nums in rn"
+ },
+ {
+ "EventName": "topdown.bad_speculation.exception_flush",
+ "EventCode": "0x00000042",
+ "BriefDescription": "Flushes generated due to exceptions"
+ },
+ {
+ "EventName": "topdown.bad_speculation.interrupt_flush",
+ "EventCode": "0x00000043",
+ "BriefDescription": "Flushes generated due to interrupts"
+ },
+ {
+ "EventName": "topdown.bad_speculation.other_flush",
+ "EventCode": "0x00000044",
+ "BriefDescription": "Other flushes generated"
+ },
+ {
+ "EventName": "inst.int.alu.spec",
+ "EventCode": "0x00000045",
+ "BriefDescription": "Completed ALU instructions"
+ },
+ {
+ "EventName": "inst.int.mul.spec",
+ "EventCode": "0x00000046",
+ "BriefDescription": "Completed MULT instructions"
+ },
+ {
+ "EventName": "inst.int.div.spec",
+ "EventCode": "0x00000047",
+ "BriefDescription": "Completed DIV instructions"
+ },
+ {
+ "EventName": "inst.int.csr.spec",
+ "EventCode": "0x00000048",
+ "BriefDescription": "Completed CSR instructions"
+ },
+ {
+ "EventName": "ieu.is.siq.stall",
+ "EventCode": "0x000000c0",
+ "BriefDescription": "cycle nums of siq full stall cycles"
+ },
+ {
+ "EventName": "ieu.is.miq.stall",
+ "EventCode": "0x000000c1",
+ "BriefDescription": "cycle nums of miq full stall cycles"
+ },
+ {
+ "EventName": "ieu.is.biq.stall",
+ "EventCode": "0x000000c2",
+ "BriefDescription": "cycle nums of biq full stall cycles"
+ },
+ {
+ "EventName": "ieu.is.lsiq.stall",
+ "EventCode": "0x000000c3",
+ "BriefDescription": "cycle nums of lsiq full stall cycles"
+ },
+ {
+ "EventName": "ieu.is.vfpq.stall",
+ "EventCode": "0x000000c4",
+ "BriefDescription": "cycle nums of fpiq full stall cycles"
+ },
+ {
+ "EventName": "topdown.backend_bound.core.div_busy",
+ "EventCode": "0x000000c5",
+ "BriefDescription": "cycle nums of div busy stall cycles"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/xuantie/c930/ifu.json b/tools/perf/pmu-events/arch/riscv/xuantie/c930/ifu.json
new file mode 100644
index 000000000000..11057f66f797
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/xuantie/c930/ifu.json
@@ -0,0 +1,62 @@
+[
+ {
+ "EventName": "inst.mispred.branch",
+ "EventCode": "0x00000018",
+ "BriefDescription": "speculative cond br mispred num"
+ },
+ {
+ "EventName": "inst.mispred.uncond_branch",
+ "EventCode": "0x00000019",
+ "BriefDescription": "speculative uncond br mispred num"
+ },
+ {
+ "EventName": "inst.mispred.ind",
+ "EventCode": "0x0000001a",
+ "BriefDescription": "speculative indir mispred num"
+ },
+ {
+ "EventName": "inst.mispred.ret",
+ "EventCode": "0x0000001b",
+ "BriefDescription": "speculative return mispred num"
+ },
+ {
+ "EventName": "inst.brjmp.branch.spec",
+ "EventCode": "0x0000001c",
+ "BriefDescription": "speculative execute cond br num"
+ },
+ {
+ "EventName": "inst.brjmp.uncond_branch.spec",
+ "EventCode": "0x0000001d",
+ "BriefDescription": "speculative execute uncond br num"
+ },
+ {
+ "EventName": "inst.brjmp.ind.spec",
+ "EventCode": "0x0000001e",
+ "BriefDescription": "speculative execute indir br num"
+ },
+ {
+ "EventName": "inst.brjmp.ret.spec",
+ "EventCode": "0x0000001f",
+ "BriefDescription": "speculative execute return num"
+ },
+ {
+ "EventName": "inst.brjmp.branch.tk",
+ "EventCode": "0x00000020",
+ "BriefDescription": "speculative br taken num"
+ },
+ {
+ "EventName": "cache.l1i.rd.miss.latency",
+ "EventCode": "0x000000b8",
+ "BriefDescription": "stall cycle because of l1 icache miss"
+ },
+ {
+ "EventName": "tlb.l1i.miss.latency",
+ "EventCode": "0x000000b9",
+ "BriefDescription": "stall cycle because of l1 itle miss"
+ },
+ {
+ "EventName": "inst.mispred.brjmp.latency",
+ "EventCode": "0x000000ba",
+ "BriefDescription": "stall cycle because of br miss"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/xuantie/c930/l2c.json b/tools/perf/pmu-events/arch/riscv/xuantie/c930/l2c.json
new file mode 100644
index 000000000000..885c554d5025
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/xuantie/c930/l2c.json
@@ -0,0 +1,87 @@
+[
+ {
+ "EventName": "cache.l2.wb",
+ "EventCode": "0x000000a2",
+ "BriefDescription": "l2 cache wb number, dirty snpresp data included."
+ },
+ {
+ "EventName": "cache.l2.rd",
+ "EventCode": "0x000000a3",
+ "BriefDescription": "l2 cache read access."
+ },
+ {
+ "EventName": "cache.l2.wr",
+ "EventCode": "0x000000a4",
+ "BriefDescription": "l2 cache store miss req from lsu."
+ },
+ {
+ "EventName": "cache.l2.refill.rd",
+ "EventCode": "0x000000a5",
+ "BriefDescription": "l2 cache refill raised by lsu/ifu."
+ },
+ {
+ "EventName": "cache.l2.refill.wr",
+ "EventCode": "0x000000a6",
+ "BriefDescription": "l2 cache refill raised by lsu stream write."
+ },
+ {
+ "EventName": "cache.l2.wb.victim",
+ "EventCode": "0x000000a7",
+ "BriefDescription": "l2 cache write back to next-level cache raised by cache replace."
+ },
+ {
+ "EventName": "cache.l2.wb.clean",
+ "EventCode": "0x000000a8",
+ "BriefDescription": "l2 cache write back to next-level cache raised by CMO or snoop."
+ },
+ {
+ "EventName": "cache.l2.inval",
+ "EventCode": "0x000000a9",
+ "BriefDescription": "l2 cache invalidation to next-level cache raised by CMO or snoop."
+ },
+ {
+ "EventName": "cache.l2.refill.inst",
+ "EventCode": "0x000000aa",
+ "BriefDescription": "l2 cache refill raised by ifu load miss."
+ },
+ {
+ "EventName": "bus.access",
+ "EventCode": "0x000000ab",
+ "BriefDescription": "bus req count."
+ },
+ {
+ "EventName": "bus.rd.access",
+ "EventCode": "0x000000ac",
+ "BriefDescription": "bus read access count."
+ },
+ {
+ "EventName": "bus.wr.access",
+ "EventCode": "0x000000af",
+ "BriefDescription": "bus evict/write access count."
+ },
+ {
+ "EventName": "topdown.backend_bound.memory.demand_read.l3",
+ "EventCode": "0x000000bb",
+ "BriefDescription": "cacheable demand read data from l3"
+ },
+ {
+ "EventName": "topdown.backend_bound.memory.demand_read.peer_core",
+ "EventCode": "0x000000bc",
+ "BriefDescription": "cacheable demand read data from peer core"
+ },
+ {
+ "EventName": "topdown.backend_bound.memory.demand_read.dram",
+ "EventCode": "0x000000bd",
+ "BriefDescription": "cacheable demand read data from dram"
+ },
+ {
+ "EventName": "topdown.backend_bound.memory.demand_ostd_read",
+ "EventCode": "0x000000be",
+ "BriefDescription": "cacheable demand read with l2 miss and already sended bus req cycle"
+ },
+ {
+ "EventName": "topdown.backend_bound.memory.demand_read",
+ "EventCode": "0x000000bf",
+ "BriefDescription": "cacheable demand read with l2 miss"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/xuantie/c930/lsu.json b/tools/perf/pmu-events/arch/riscv/xuantie/c930/lsu.json
new file mode 100644
index 000000000000..5779692951e4
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/xuantie/c930/lsu.json
@@ -0,0 +1,182 @@
+[
+ {
+ "EventName": "topdown.backend_bound.memory.store.l2_miss",
+ "EventCode": "0x00000079",
+ "BriefDescription": "store l2 miss and results in issue block"
+ },
+ {
+ "EventName": "topdown.backend_bound.memory.store.l1_miss",
+ "EventCode": "0x0000007a",
+ "BriefDescription": "store l1 miss and results in issue block"
+ },
+ {
+ "EventName": "topdown.backend_bound.memory.load.l2_miss",
+ "EventCode": "0x0000007b",
+ "BriefDescription": "load l2 miss and results in issue block"
+ },
+ {
+ "EventName": "topdown.backend_bound.memory.load.l1_miss",
+ "EventCode": "0x0000007c",
+ "BriefDescription": "load l1 miss and results in issue block"
+ },
+ {
+ "EventName": "topdown.backend_bound.memory.load.struct_hazard",
+ "EventCode": "0x0000007d",
+ "BriefDescription": "load struct hazards and results in issue block"
+ },
+ {
+ "EventName": "topdown.bad_speculation.rar_hazard_early_flush",
+ "EventCode": "0x0000007e",
+ "BriefDescription": "rar hazard results in early flush"
+ },
+ {
+ "EventName": "topdown.bad_speculation.rar_hazard_abnr_flush",
+ "EventCode": "0x0000007f",
+ "BriefDescription": "rar hazard results in retire flush"
+ },
+ {
+ "EventName": "topdown.bad_speculation.raw_hazard_early_flush",
+ "EventCode": "0x00000080",
+ "BriefDescription": "raw hazard results in early flush"
+ },
+ {
+ "EventName": "topdown.bad_speculation.raw_hazard_abnr_flush",
+ "EventCode": "0x00000081",
+ "BriefDescription": "raw hazard results in retire flush"
+ },
+ {
+ "EventName": "inst.load.unalign",
+ "EventCode": "0x00000083",
+ "BriefDescription": "load unalign split"
+ },
+ {
+ "EventName": "inst.store.unalign",
+ "EventCode": "0x00000084",
+ "BriefDescription": "store unalign split"
+ },
+ {
+ "EventName": "cache.l1d.wr.access",
+ "EventCode": "0x0000008a",
+ "BriefDescription": "store access l1 dcache"
+ },
+ {
+ "EventName": "cache.l1d.wr.miss",
+ "EventCode": "0x0000008b",
+ "BriefDescription": "store l1 dcache miss"
+ },
+ {
+ "EventName": "cache.l1d.refill.inner",
+ "EventCode": "0x0000008c",
+ "BriefDescription": "l1 dcache miss and l2c hit"
+ },
+ {
+ "EventName": "cache.l1d.refill.outer",
+ "EventCode": "0x0000008d",
+ "BriefDescription": "l1 dcache miss and l2c miss"
+ },
+ {
+ "EventName": "cache.l1d.wb",
+ "EventCode": "0x0000008e",
+ "BriefDescription": "l1 dcache dirty line eviction"
+ },
+ {
+ "EventName": "cache.l1d.wb.victim",
+ "EventCode": "0x0000008f",
+ "BriefDescription": "l1 dcache dirty line evicted by new cache line refill"
+ },
+ {
+ "EventName": "cache.l1d.wb.clean",
+ "EventCode": "0x00000090",
+ "BriefDescription": "l1 dcache dirty line evicted by cmo or snoop"
+ },
+ {
+ "EventName": "cache.l1d.inval",
+ "EventCode": "0x00000091",
+ "BriefDescription": "l1 dcache line invalidated by cmo or snoop"
+ },
+ {
+ "EventName": "inst.ldst.load.spec",
+ "EventCode": "0x00000092",
+ "BriefDescription": "load inst, not include prefetch"
+ },
+ {
+ "EventName": "inst.ldst.store.spec",
+ "EventCode": "0x00000093",
+ "BriefDescription": "store inst, not include cmo"
+ },
+ {
+ "EventName": "inst.ldst.lr.spec",
+ "EventCode": "0x00000094",
+ "BriefDescription": "lr inst"
+ },
+ {
+ "EventName": "inst.ldst.sc",
+ "EventCode": "0x00000095",
+ "BriefDescription": "sc inst"
+ },
+ {
+ "EventName": "inst.ldst.sc.pass",
+ "EventCode": "0x00000096",
+ "BriefDescription": "sc pass"
+ },
+ {
+ "EventName": "inst.ldst.sc.fail",
+ "EventCode": "0x00000097",
+ "BriefDescription": "sc fail"
+ },
+ {
+ "EventName": "inst.ldst.amo",
+ "EventCode": "0x00000098",
+ "BriefDescription": "amo inst"
+ },
+ {
+ "EventName": "inst.ldst.load_acquire.spec",
+ "EventCode": "0x00000099",
+ "BriefDescription": "load acquire inst"
+ },
+ {
+ "EventName": "inst.ldst.store_release.spec",
+ "EventCode": "0x0000009a",
+ "BriefDescription": "store release inst"
+ },
+ {
+ "EventName": "inst.ldst.fence",
+ "EventCode": "0x0000009b",
+ "BriefDescription": "fence inst"
+ },
+ {
+ "EventName": "inst.ldst.fencei",
+ "EventCode": "0x0000009c",
+ "BriefDescription": "fencei inst"
+ },
+ {
+ "EventName": "inst.ldst.dvm_sync",
+ "EventCode": "0x0000009d",
+ "BriefDescription": "dvm sync inst"
+ },
+ {
+ "EventName": "inst.ldst.vec_load.spec",
+ "EventCode": "0x0000009e",
+ "BriefDescription": "vector load inst(each split inst counts 1)"
+ },
+ {
+ "EventName": "inst.ldst.vec_store.spec",
+ "EventCode": "0x0000009f",
+ "BriefDescription": "vector store inst(each split inst counts 1)"
+ },
+ {
+ "EventName": "inst.ldst.float_load.spec",
+ "EventCode": "0x000000a0",
+ "BriefDescription": "float load inst"
+ },
+ {
+ "EventName": "inst.ldst.float_store.spec",
+ "EventCode": "0x000000a1",
+ "BriefDescription": "float store inst"
+ },
+ {
+ "EventName": "inst.ldst.spec",
+ "EventCode": "0x000000b3",
+ "BriefDescription": "lsu inst cmplt num"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/xuantie/c930/vfpu.json b/tools/perf/pmu-events/arch/riscv/xuantie/c930/vfpu.json
new file mode 100644
index 000000000000..4412e4acc817
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/xuantie/c930/vfpu.json
@@ -0,0 +1,177 @@
+[
+ {
+ "EventName": "vfpu_ex1_rep",
+ "EventCode": "0x00000059",
+ "BriefDescription": "Number of inst replayed in VFPU EX1 stage"
+ },
+ {
+ "EventName": "topdown.backend_bound.core.rvv_stall",
+ "EventCode": "0x0000005a",
+ "BriefDescription": "Number of stall cycles caused by vfpu blocking execution instructions"
+ },
+ {
+ "EventName": "inst.sca.fp.arith.spec",
+ "EventCode": "0x0000005b",
+ "BriefDescription": "Number of executed scalar floating-point instructions"
+ },
+ {
+ "EventName": "inst.fp.arith.half.spec",
+ "EventCode": "0x0000005c",
+ "BriefDescription": "Number of executed half-precision scalar floating-point micro-instructions"
+ },
+ {
+ "EventName": "inst.fp.arith.single.spec",
+ "EventCode": "0x0000005d",
+ "BriefDescription": "Number of executed single-precision scalar floating-point micro-instructions"
+ },
+ {
+ "EventName": "inst.fp.arith.double.spec",
+ "EventCode": "0x0000005e",
+ "BriefDescription": "Number of executed double-precision scalar floating-point micro-instructions"
+ },
+ {
+ "EventName": "inst.rvv.arith.spec",
+ "EventCode": "0x0000005f",
+ "BriefDescription": "Number of executed vector macro-instructions"
+ },
+ {
+ "EventName": "uop.rvv.arith.spec",
+ "EventCode": "0x00000060",
+ "BriefDescription": "Number of executed vector micro-instructions"
+ },
+ {
+ "EventName": "uop.rvv.arith.fp.spec",
+ "EventCode": "0x00000061",
+ "BriefDescription": "Number of executed vector floating-point micro-instructions"
+ },
+ {
+ "EventName": "inst.rvv.arith.fp.spec",
+ "EventCode": "0x00000062",
+ "BriefDescription": "Number of executed vector floating-point macro-instructions"
+ },
+ {
+ "EventName": "uop.sca.fp.arith.bf.spec",
+ "EventCode": "0x00000063",
+ "BriefDescription": "Number of executed bfloat16 micro-instructions"
+ },
+ {
+ "EventName": "uop.rvv.arith.vint8.spec",
+ "EventCode": "0x00000064",
+ "BriefDescription": "Number of vector micro-instructions executed with source operands of type int8"
+ },
+ {
+ "EventName": "uop.rvv.arith.vint16.spec",
+ "EventCode": "0x00000065",
+ "BriefDescription": "Number of vector micro-instructions executed with source operands of type int16"
+ },
+ {
+ "EventName": "uop.rvv.arith.vint32.spec",
+ "EventCode": "0x00000066",
+ "BriefDescription": "Number of vetor micro-instructions executed with source operands of type int32"
+ },
+ {
+ "EventName": "uop.rvv.arith.vint64.spec",
+ "EventCode": "0x00000067",
+ "BriefDescription": "Number of vector micro-instructions executed with source operands of type int64"
+ },
+ {
+ "EventName": "uop.rvv.arith.fix_point.spec",
+ "EventCode": "0x00000068",
+ "BriefDescription": "Number of executed fixed-point micro-instructions"
+ },
+ {
+ "EventName": "uop.fp.arith.fdiv.spec",
+ "EventCode": "0x00000069",
+ "BriefDescription": "Number of executed floting-point division micro-instructions"
+ },
+ {
+ "EventName": "uop.rvv.arith.idiv.spec",
+ "EventCode": "0x0000006a",
+ "BriefDescription": "Number of executed integer division micro-instructions"
+ },
+ {
+ "EventName": "uop.rvv.arith.zvkn.spec",
+ "EventCode": "0x0000006b",
+ "BriefDescription": "Number of executed ZVKN-extension micro-instructions"
+ },
+ {
+ "EventName": "uop.rvv.arith.zvks.spec",
+ "EventCode": "0x0000006c",
+ "BriefDescription": "Number of executed ZVKS-extension micro-instructions"
+ },
+ {
+ "EventName": "uop.rvv.arith.vmulu64.spec",
+ "EventCode": "0x0000006d",
+ "BriefDescription": "Number of micro-instructions executed in vector 64-bit integer multiplication unit"
+ },
+ {
+ "EventName": "uop.rvv.arith.vmulu.spec",
+ "EventCode": "0x0000006e",
+ "BriefDescription": "Number of micro-instructions executed in vector integer multiplication unit"
+ },
+ {
+ "EventName": "uop.rvv.arith.vdot.spec",
+ "EventCode": "0x0000006f",
+ "BriefDescription": "Number of executed RISC-V and Xuantie dot-extension micro-instructions"
+ },
+ {
+ "EventName": "uop.rvv.arith.vfmul.spec",
+ "EventCode": "0x00000070",
+ "BriefDescription": "Number of executed floating-point multiplication micro-instructions"
+ },
+ {
+ "EventName": "uop.rvv.arith.vfadd.spec",
+ "EventCode": "0x00000071",
+ "BriefDescription": "Number of executed floating-point addition micro-instructions"
+ },
+ {
+ "EventName": "uop.rvv.arith.perm.spec",
+ "EventCode": "0x00000072",
+ "BriefDescription": "Number of executed permutation micro-instructions"
+ },
+ {
+ "EventName": "uop.rvv.arith.redu.spec",
+ "EventCode": "0x00000073",
+ "BriefDescription": "Number of executed integer reduction micro-instructions"
+ },
+ {
+ "EventName": "uop.rvv.arith.fred.spec",
+ "EventCode": "0x00000074",
+ "BriefDescription": "Number of executed floating-point reduction micro-instructions"
+ },
+ {
+ "EventName": "uop.rvv.arith.mask.spec",
+ "EventCode": "0x00000075",
+ "BriefDescription": "Number of executed vector masked micro-instructions"
+ },
+ {
+ "EventName": "uop.rvv.arith.vlmax.spec",
+ "EventCode": "0x00000076",
+ "BriefDescription": "Number of vector micro-instructions excuted with max number of element"
+ },
+ {
+ "EventName": "uop.rvv.arith.agnostic.spec",
+ "EventCode": "0x00000077",
+ "BriefDescription": "Number of vector micro-instructions excuted with agnostic policy"
+ },
+ {
+ "EventName": "uop.rvv.arith.idiv_direct.spec",
+ "EventCode": "0x00000078",
+ "BriefDescription": "Number of vector integer division micro-instructions producing special value types"
+ },
+ {
+ "EventName": "uop.rvv.vadd.spec",
+ "EventCode": "0x000000ae",
+ "BriefDescription": "Number of executed vector integer addition micro-instructions"
+ },
+ {
+ "EventName": "uop.rvv.vmacc.spec",
+ "EventCode": "0x000000af",
+ "BriefDescription": "Number of executed vector integer multiply-add micro-instructions"
+ },
+ {
+ "EventName": "uop.rvv.vfmacc.spec",
+ "EventCode": "0x000000b0",
+ "BriefDescription": "Number of executed vector floating-point multiply-add micro-instructions"
+ }
+]
--
2.50.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 4/4] perf vendor events riscv: Add XuanTie C930 metrics
2025-11-21 6:34 [PATCH v2 0/4] perf vendor events riscv: Add XuanTie C930 JSON files cp0613
` (2 preceding siblings ...)
2025-11-21 6:34 ` [PATCH v2 3/4] perf vendor events riscv: Add XuanTie C930 JSON file cp0613
@ 2025-11-21 6:34 ` cp0613
2025-11-21 9:02 ` Krzysztof Kozlowski
3 siblings, 1 reply; 13+ messages in thread
From: cp0613 @ 2025-11-21 6:34 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, pjw, palmer, aou, peterz, mingo, acme,
namhyung, mark.rutland, alexander.shishkin, jolsa, irogers,
adrian.hunter, james.clark, guoren
Cc: devicetree, linux-perf-users, linux-riscv, linux-kernel, Chen Pei
From: Chen Pei <cp0613@linux.alibaba.com>
This patch adds XuanTie C930 metrics, including topdown and some
other metric groups.
Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
---
.../arch/riscv/xuantie/c930/metrics.json | 538 ++++++++++++++++++
1 file changed, 538 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/riscv/xuantie/c930/metrics.json
diff --git a/tools/perf/pmu-events/arch/riscv/xuantie/c930/metrics.json b/tools/perf/pmu-events/arch/riscv/xuantie/c930/metrics.json
new file mode 100644
index 000000000000..689bae6209dc
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/xuantie/c930/metrics.json
@@ -0,0 +1,538 @@
+[
+ {
+ "MetricExpr": "(topdown.frontend_bound.slots - topdown.bad_speculation.recovery_bubbles*8) / topdown.slots ",
+ "PublicDescription": "Fraction of slots unused due to the frontend's inability to supply enough uops",
+ "BriefDescription": "Fraction of slots unused due to the frontend's inability to supply enough uops",
+ "CommonMetricgroupName": "TopdownL1",
+ "MetricGroup": "Common;TopdownL1",
+ "MetricName": "topdown.frontend_bound.rate"
+ },
+ {
+ "MetricExpr": "(uop.spec - uop.ret + topdown.bad_speculation.recovery_bubbles*8) / topdown.slots",
+ "PublicDescription": "Fraction of slots wasted due to incorrect speculations",
+ "BriefDescription": "Fraction of slots wasted due to incorrect speculations",
+ "CommonMetricgroupName": "TopdownL1",
+ "MetricGroup": "Common;TopdownL1",
+ "MetricName": "topdown.bad_speculation.rate"
+ },
+ {
+ "MetricExpr": "uop.ret / topdown.slots",
+ "PublicDescription": "Fraction of slots that retired",
+ "BriefDescription": "Fraction of slots that retired",
+ "CommonMetricgroupName": "TopdownL1",
+ "MetricGroup": "Common;TopdownL1",
+ "MetricName": "topdown.retiring.rate"
+ },
+ {
+ "MetricExpr": "1 - (topdown.frontend_bound.rate + topdown.bad_speculation.rate + topdown.retiring.rate)",
+ "PublicDescription": "Fraction of slots unused due to a lack of backend resources",
+ "BriefDescription": "Fraction of slots unused due to a lack of backend resources",
+ "CommonMetricgroupName": "TopdownL1",
+ "MetricGroup": "Common;TopdownL1",
+ "MetricName": "topdown.backend_bound.rate"
+ },
+ {
+ "MetricExpr": "topdown.frontend_bound.latency.slots / topdown.slots",
+ "PublicDescription": "Fetch latency bound L2 topdown metric",
+ "BriefDescription": "Fetch latency bound L2 topdown metric",
+ "MetricGroup": "TopdownL2",
+ "MetricName": "topdown.frontend_bound.latency.rate"
+ },
+ {
+ "MetricExpr": "topdown.frontend_bound.rate - topdown.frontend_bound.latency.rate",
+ "PublicDescription": "Fetch bandwidth bound L2 topdown metric",
+ "BriefDescription": "Fetch bandwidth bound L2 topdown metric",
+ "MetricGroup": "TopdownL2",
+ "MetricName": "topdown.frontend_bound.bandwidth.rate"
+ },
+ {
+ "MetricExpr": "topdown.bad_speculation.rate * inst.mispred.brjmp.spec / (inst.mispred.brjmp.spec + topdown.bad_speculation.exception_flush + topdown.bad_speculation.interrupt_flush + topdown.bad_speculation.other_flush + topdown.bad_speculation.rar_hazard_early_flush + topdown.bad_speculation.raw_hazard_early_flush)",
+ "PublicDescription": "Branch mispredicts L2 topdown metric",
+ "BriefDescription": "Branch mispredicts L2 topdown metric",
+ "MetricGroup": "TopdownL2",
+ "MetricName": "topdown.bad_speculation.branch_mispredicts.rate"
+ },
+ {
+ "MetricExpr": "topdown.bad_speculation.rate * (topdown.bad_speculation.raw_hazard_early_flush + topdown.bad_speculation.rar_hazard_early_flush) / (inst.mispred.brjmp.spec + topdown.bad_speculation.exception_flush + topdown.bad_speculation.interrupt_flush + topdown.bad_speculation.other_flush + topdown.bad_speculation.rar_hazard_early_flush + topdown.bad_speculation.raw_hazard_early_flush)",
+ "PublicDescription": "Load/Store early flush L2 topdown metric",
+ "BriefDescription": "Load/Store early flush L2 topdown metric",
+ "MetricGroup": "TopdownL2",
+ "MetricName": "topdown.bad_speculation.ldst_early_flush.rate"
+ },
+ {
+ "MetricExpr": "topdown.bad_speculation.rate - (topdown.bad_speculation.branch_mispredicts.rate + topdown.bad_speculation.ldst_early_flush.rate)",
+ "PublicDescription": "Machine clears L2 topdown metric",
+ "BriefDescription": "Machine clears L2 topdown metric",
+ "MetricGroup": "TopdownL2",
+ "MetricName": "topdown.bad_speculation.machine_clears.rate"
+ },
+ {
+ "MetricExpr": "topdown.backend_bound.rate * (topdown.backend_bound.memory.load + topdown.backend_bound.memory.store)/cycles.hart",
+ "PublicDescription": "Memory bound L2 topdown metric",
+ "BriefDescription": "Memory bound L2 topdown metric",
+ "MetricGroup": "TopdownL2",
+ "MetricName": "topdown.backend_bound.memory_bound.rate"
+ },
+ {
+ "MetricExpr": "topdown.backend_bound.rate - topdown.backend_bound.memory_bound.rate",
+ "PublicDescription": "Core bound L2 topdown metric",
+ "BriefDescription": "Core bound L2 topdown metric",
+ "MetricGroup": "TopdownL2",
+ "MetricName": "topdown.backend_bound.core_bound.rate"
+ },
+ {
+ "MetricExpr": "topdown.retiring.rate * (inst.int.alu.spec + inst.int.mul.spec + inst.int.div.spec + inst.int.csr.spec) / uop.spec",
+ "PublicDescription": "Integer operations L2 topdown metric",
+ "BriefDescription": "Integer operations L2 topdown metric",
+ "MetricGroup": "TopdownL2",
+ "MetricName": "topdown.retiring.int.rate"
+ },
+ {
+ "MetricExpr": "topdown.retiring.rate * inst.brjmp.spec / uop.spec",
+ "PublicDescription": "Branch operations L2 topdown metric",
+ "BriefDescription": "Branch operations L2 topdown metric",
+ "MetricGroup": "TopdownL2",
+ "MetricName": "topdown.retiring.brjmp.rate"
+ },
+ {
+ "MetricExpr": "topdown.retiring.rate * inst.ldst.spec / uop.spec",
+ "PublicDescription": "Load/Store operations L2 topdown metric",
+ "BriefDescription": "Load/Store operations L2 topdown metric",
+ "MetricGroup": "TopdownL2",
+ "MetricName": "topdown.retiring.ldst.rate"
+ },
+ {
+ "MetricExpr": "topdown.retiring.rate * inst.sca.fp.arith.spec / uop.spec",
+ "PublicDescription": "Scalar float point arithmetic operations L2 topdown metric",
+ "BriefDescription": "Scalar float point arithmetic operations L2 topdown metric",
+ "MetricGroup": "TopdownL2",
+ "MetricName": "topdown.retiring.fp.arith.rate"
+ },
+ {
+ "MetricExpr": "topdown.retiring.rate * inst.rvv.arith.spec / uop.spec",
+ "PublicDescription": "Vector arithmetic operations L2 topdown metric",
+ "BriefDescription": "Vector arithmetic operations L2 topdown metric",
+ "MetricGroup": "TopdownL2",
+ "MetricName": "topdown.retiring.rvv.arith.rate"
+ },
+ {
+ "MetricExpr": "topdown.retiring.rate - topdown.retiring.int.rate - topdown.retiring.brjmp.rate - topdown.retiring.ldst.rate - topdown.retiring.fp.arith.rate - topdown.retiring.rvv.arith.rate",
+ "PublicDescription": "Other operations L2 topdown metric",
+ "BriefDescription": "Other operations L2 topdown metric",
+ "MetricGroup": "TopdownL2",
+ "MetricName": "topdown.retiring.other.rate"
+ },
+ {
+ "MetricExpr": "cache.l1i.rd.miss.latency / cycles.hart",
+ "PublicDescription": "Idle by icache miss L3 topdown metric",
+ "BriefDescription": "Idle by icache miss L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.frontend_bound.latency.data.rate"
+ },
+ {
+ "MetricExpr": "tlb.l1i.miss.latency / cycles.hart",
+ "PublicDescription": "Idle by itlb miss L3 topdown metric",
+ "BriefDescription": "Idle by itlb miss L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.frontend_bound.latency.addr.rate"
+ },
+ {
+ "MetricExpr": "inst.mispred.brjmp.latency / cycles.hart",
+ "PublicDescription": "Idle by fetch pipeline bubbles L3 topdown metric",
+ "BriefDescription": "Idle by fetch pipeline bubbles L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.frontend_bound.latency.redirect.rate"
+ },
+ {
+ "MetricExpr": "inst.mispred.brjmp.spec / inst.brjmp.spec",
+ "PublicDescription": "Branch misprediction rate L3 topdown metric",
+ "BriefDescription": "Branch misprediction rate L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "inst.mispred.rate"
+ },
+ {
+ "MetricExpr": "inst.mispred.brjmp.spec * 1000 / uop.spec",
+ "PublicDescription": "Branch misprediction per 1000 instructions L3 topdown metric",
+ "BriefDescription": "Branch misprediction per 1000 instructions L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "inst.mispred.pki"
+ },
+ {
+ "MetricExpr": "inst.mispred.branch / inst.brjmp.branch.spec",
+ "PublicDescription": "Condition branch misprediction rate L3 topdown metric",
+ "BriefDescription": "Condition branch misprediction rate L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "inst.mispred.branch.rate"
+ },
+ {
+ "MetricExpr": "inst.mispred.branch *1000 / uop.spec",
+ "PublicDescription": "Condition branch misprediction per 1000 instructions L3 topdown metric",
+ "BriefDescription": "Condition branch misprediction per 1000 instructions L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "inst.mispred.branch.pki"
+ },
+ {
+ "MetricExpr": "inst.mispred.uncond_branch / inst.brjmp.uncond_branch.spec",
+ "PublicDescription": "Unconditional branch (exclude indirect branch and function return) misprediction rate L3 topdown metric",
+ "BriefDescription": "Unconditional branch (exclude indirect branch and function return) misprediction rate L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "inst.mispred.uncond_branch.rate"
+ },
+ {
+ "MetricExpr": "inst.mispred.uncond_branch *1000 / uop.spec",
+ "PublicDescription": "Unconditional branch (exclude indirect branch and function return) misprediction per 1000 instructions L3 topdown metric",
+ "BriefDescription": "Unconditional branch (exclude indirect branch and function return) misprediction per 1000 instructions L3 topdown metric",
+ "MetricGroup": "TopdownL3;Per-instruction",
+ "MetricName": "inst.mispred.uncond_branch.pki"
+ },
+ {
+ "MetricExpr": "inst.mispred.ind / inst.brjmp.ind.spec",
+ "PublicDescription": "Indirect branch misprediction rate L3 topdown metric",
+ "BriefDescription": "Indirect branch misprediction rate L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "inst.mispred.ind.rate"
+ },
+ {
+ "MetricExpr": "inst.mispred.ind *1000 / uop.spec",
+ "PublicDescription": "Indirect branch misprediction per 1000 instructions L3 topdown metric",
+ "BriefDescription": "Indirect branch misprediction per 1000 instructions L3 topdown metric",
+ "MetricGroup": "TopdownL3;Per-instruction",
+ "MetricName": "inst.mispred.ind.pki"
+ },
+ {
+ "MetricExpr": "inst.mispred.ret / inst.brjmp.ret.spec",
+ "PublicDescription": "Function return misprediction rate L3 topdown metric",
+ "BriefDescription": "Function return misprediction rate L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "inst.mispred.ret.rate"
+ },
+ {
+ "MetricExpr": "inst.mispred.ret *1000 / uop.spec",
+ "PublicDescription": "Function return misprediction per 1000 instructions L3 topdown metric",
+ "BriefDescription": "Function return misprediction per 1000 instructions L3 topdown metric",
+ "MetricGroup": "TopdownL3;Per-instruction",
+ "MetricName": "inst.mispred.ret.pki"
+ },
+ {
+ "MetricExpr": "topdown.bad_speculation.raw_hazard_early_flush / (topdown.bad_speculation.raw_hazard_early_flush + topdown.bad_speculation.rar_hazard_early_flush)",
+ "PublicDescription": "RAW early flush rate L3 topdown metric",
+ "BriefDescription": "RAW early flush rate L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.bad_speculation.raw_hazard_early_flush.rate"
+ },
+ {
+ "MetricExpr": "topdown.bad_speculation.rar_hazard_early_flush / (topdown.bad_speculation.raw_hazard_early_flush + topdown.bad_speculation.rar_hazard_early_flush)",
+ "PublicDescription": "RAR early flush rate L3 topdown metric",
+ "BriefDescription": "RAR early flush rate L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.bad_speculation.rar_hazard_early_flush.rate"
+ },
+ {
+ "MetricExpr": "topdown.bad_speculation.exception_flush / (topdown.bad_speculation.exception_flush + topdown.bad_speculation.interrupt_flush + topdown.bad_speculation.other_flush)",
+ "PublicDescription": "exception flush rate L3 topdown metric",
+ "BriefDescription": "exception flush rate L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.bad_speculation.exception_flush.rate"
+ },
+ {
+ "MetricExpr": "topdown.bad_speculation.interrupt_flush / (topdown.bad_speculation.exception_flush + topdown.bad_speculation.interrupt_flush + topdown.bad_speculation.other_flush)",
+ "PublicDescription": "interrupt flush rate L3 topdown metric",
+ "BriefDescription": "interrupt flush rate L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.bad_speculation.interrupt_flush.rate"
+ },
+ {
+ "MetricExpr": "topdown.bad_speculation.other_flush / (topdown.bad_speculation.exception_flush + topdown.bad_speculation.interrupt_flush + topdown.bad_speculation.other_flush)",
+ "PublicDescription": "other flush rate L3 topdown metric",
+ "BriefDescription": "other flush rate L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.bad_speculation.other_flush.rate"
+ },
+ {
+ "MetricExpr": "topdown.retiring.rate * inst.int.alu.spec / uop.spec",
+ "PublicDescription": "Arithmetic operations L3 topdown metric",
+ "BriefDescription": "Arithmetic operations L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.retiring.int.alu.rate"
+ },
+ {
+ "MetricExpr": "topdown.retiring.rate * inst.int.mul.spec / uop.spec",
+ "PublicDescription": "Multiplication operations L3 topdown metric",
+ "BriefDescription": "Multiplication operations L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.retiring.int.mul.rate"
+ },
+ {
+ "MetricExpr": "topdown.retiring.rate * inst.int.div.spec / uop.spec",
+ "PublicDescription": "Division operations L3 topdown metric",
+ "BriefDescription": "Division operations L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.retiring.int.div.rate"
+ },
+ {
+ "MetricExpr": "topdown.retiring.rate * inst.int.csr.spec / uop.spec",
+ "PublicDescription": "CSR access operations L3 topdown metric",
+ "BriefDescription": "CSR access operations L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.retiring.int.csr.rate"
+ },
+ {
+ "MetricExpr": "topdown.retiring.rate * inst.brjmp.branch.spec / uop.spec",
+ "PublicDescription": "Conditional branch operations L3 topdown metric",
+ "BriefDescription": "Conditional branch operations L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.retiring.brjmp.branch.rate"
+ },
+ {
+ "MetricExpr": "topdown.retiring.rate * inst.brjmp.ind.spec / uop.spec",
+ "PublicDescription": "Indirect branch operations L3 topdown metric",
+ "BriefDescription": "Indirect branch operations L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.retiring.brjmp.ind.rate"
+ },
+ {
+ "MetricExpr": "topdown.retiring.rate * inst.brjmp.ret.spec / uop.spec",
+ "PublicDescription": "Function return operations L3 topdown metric",
+ "BriefDescription": "Function return operations L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.retiring.brjmp.ret.rate"
+ },
+ {
+ "MetricExpr": "topdown.retiring.rate * inst.brjmp.uncond_branch.spec / uop.spec",
+ "PublicDescription": "Unconditional branch operations L3 topdown metric",
+ "BriefDescription": "Unconditional branch operations L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.retiring.brjmp.uncond_branch.rate"
+ },
+ {
+ "MetricExpr": "topdown.retiring.rate * inst.ldst.load.spec / uop.spec",
+ "PublicDescription": "Load operations L3 topdown metric",
+ "BriefDescription": "Load operations L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.retiring.ldst.load.rate"
+ },
+ {
+ "MetricExpr": "topdown.retiring.rate * inst.ldst.store.spec / uop.spec",
+ "PublicDescription": "Store operations L3 topdown metric",
+ "BriefDescription": "Store operations L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.retiring.ldst.store.rate"
+ },
+ {
+ "MetricExpr": "topdown.retiring.rate * inst.ldst.float_load.spec / uop.spec",
+ "PublicDescription": "Float load operations L3 topdown metric",
+ "BriefDescription": "Float laod operations L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.retiring.ldst.float_load.rate"
+ },
+ {
+ "MetricExpr": "topdown.retiring.rate * inst.ldst.float_store.spec / uop.spec",
+ "PublicDescription": "Float store operations L3 topdown metric",
+ "BriefDescription": "Float store operations L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.retiring.ldst.float_store.rate"
+ },
+ {
+ "MetricExpr": "topdown.retiring.rate * inst.ldst.vec_load.spec / uop.spec",
+ "PublicDescription": "Vector load operations L3 topdown metric",
+ "BriefDescription": "Vector load operations L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.retiring.ldst.vec_load.rate"
+ },
+ {
+ "MetricExpr": "topdown.retiring.rate * inst.ldst.vec_store.spec / uop.spec",
+ "PublicDescription": "Vector store operations L3 topdown metric",
+ "BriefDescription": "Vector store operations L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.retiring.ldst.vec_store.rate"
+ },
+ {
+ "MetricExpr": "topdown.backend_bound.core.barrier_csr / cycles.hart",
+ "PublicDescription": "Core bound barrier stall L3 topdown metric",
+ "BriefDescription": "Core bound barrier stall L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.backend_bound.core.barrier.rate"
+ },
+ {
+ "MetricExpr": "topdown.backend_bound.core.highload / cycles.hart",
+ "PublicDescription": "Core bound high load stall L3 topdown metric",
+ "BriefDescription": "Core bound high load stall L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.backend_bound.core.highload.rate"
+ },
+ {
+ "MetricExpr": "topdown.backend_bound.core.rob_full / cycles.hart",
+ "PublicDescription": "Core bound rob full stall L3 topdown metric",
+ "BriefDescription": "Core bound rob full stall L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.backend_bound.core.rob_full.rate"
+ },
+ {
+ "MetricExpr": " (ieu.is.siq.stall + ieu.is.miq.stall + ieu.is.biq.stall + ieu.is.lsiq.stall + ieu.is.vfpq.stall) / cycles.hart",
+ "PublicDescription": "Core bound issue queue stall L3 topdown metric",
+ "BriefDescription": "Core bound issueu queue stall L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.backend_bound.core.is_stall.rate"
+ },
+ {
+ "MetricExpr": " topdown.backend_bound.core.div_busy / cycles.hart",
+ "PublicDescription": "Core bound div busy stall L3 topdown metric",
+ "BriefDescription": "Core bound div busy stall L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.backend_bound.core.div_busy.rate"
+ },
+ {
+ "MetricExpr": " topdown.backend_bound.core.rvv_stall / cycles.hart",
+ "PublicDescription": "Core bound rvv stall L3 topdown metric",
+ "BriefDescription": "Core bound rvv stall L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.backend_bound.core.rvv_stall.rate"
+ },
+ {
+ "MetricExpr": "topdown.backend_bound.memory.load.l2_miss / (topdown.backend_bound.memory.load + topdown.backend_bound.memory.store)",
+ "PublicDescription": "External memory bound L3 topdown metric",
+ "BriefDescription": "External memory bound L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.backend_bound.memory.ext_mem_bound.rate"
+ },
+ {
+ "MetricExpr": "topdown.backend_bound.memory.load.l1_miss / (topdown.backend_bound.memory.load + topdown.backend_bound.memory.store)",
+ "PublicDescription": "L2 memory bound L3 topdown metric",
+ "BriefDescription": "L2 memory bound L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.backend_bound.memory.l2_bound.rate"
+ },
+ {
+ "MetricExpr": "1 - topdown.backend_bound.memory.ext_mem_bound.rate - topdown.backend_bound.memory.l2_bound.rate - topdown.backend_bound.memory.store_bound.rate",
+ "PublicDescription": "L1 memory bound L3 topdown metric",
+ "BriefDescription": "L1 memory bound L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.backend_bound.memory.l1_bound.rate"
+ },
+ {
+ "MetricExpr": "topdown.backend_bound.memory.store / (topdown.backend_bound.memory.load + topdown.backend_bound.memory.store)",
+ "PublicDescription": "Store bound L3 topdown metric",
+ "BriefDescription": "Store bound L3 topdown metric",
+ "MetricGroup": "TopdownL3",
+ "MetricName": "topdown.backend_bound.memory.store_bound.rate"
+ },
+ {
+ "MetricExpr": "cycles.hart * 8",
+ "PublicDescription": "Total slots",
+ "BriefDescription": "Total slots",
+ "MetricGroup": "Common",
+ "MetricName": "topdown.slots"
+ },
+ {
+ "MetricExpr": "uop.ret / cycles.hart",
+ "PublicDescription": "Instructions per cycle",
+ "BriefDescription": "Instructions per cycle",
+ "MetricGroup": "Common;Per-cycle",
+ "MetricName": "ipc"
+ },
+ {
+ "MetricExpr": "cache.l1d.rd.miss * 1000 / uop.ret",
+ "PublicDescription": "l1 dcache access misses per 1000 instructions",
+ "BriefDescription": "l1 dcache access misses per 1000 instructions",
+ "MetricGroup": "Common;Per-instruction",
+ "MetricName": "cache.l1d.rd.data.mpki"
+ },
+ {
+ "MetricExpr": "cache.l1d.wr.miss * 1000 / uop.ret",
+ "PublicDescription": "l1 dcache write access misses per 1000 instructions",
+ "BriefDescription": "l1 dcache write access misses per 1000 instructions",
+ "MetricGroup": "Common;Per-instruction",
+ "MetricName": "cache.l1d.wr.data.mpki"
+ },
+ {
+ "MetricExpr": "cache.l1i.rd.miss * 1000 / uop.ret",
+ "PublicDescription": "l1 icache access misses per 1000 instructions",
+ "BriefDescription": "l1 icache access misses per 1000 instructions",
+ "MetricGroup": "Common;Per-instruction",
+ "MetricName": "cache.l1i.rd.code.mpki"
+ },
+ {
+ "MetricExpr": "cache.l2.miss * 1000 / uop.ret",
+ "PublicDescription": "l2 cache access misses per 1000 instructions",
+ "BriefDescription": "l2 cache access misses per 1000 instructions",
+ "MetricGroup": "Common;Per-instruction",
+ "MetricName": "cache.l2.mpki"
+ },
+ {
+ "MetricExpr": "tlb.l1d.miss * 1000 / uop.ret",
+ "PublicDescription": "L1 TLB misses caused by data loads or stores per 1000 instructions",
+ "BriefDescription": "L1 TLB misses caused by data loads or stores per 1000 instructions",
+ "MetricGroup": "Common;Per-instruction",
+ "MetricName": "tlb.l1d.ldst.mpki"
+ },
+ {
+ "MetricExpr": "tlb.l1i.miss * 1000 / uop.ret",
+ "PublicDescription": "L1 TLB misses caused by instruction fetch per 1000 instructions",
+ "BriefDescription": "L1 TLB misses caused by instruction fetch per 1000 instructions",
+ "MetricGroup": "Common;Per-instruction",
+ "MetricName": "tlb.l1i.code.mpki"
+ },
+ {
+ "MetricExpr": "cache.l1d.rd.miss / cache.l1d.rd.access",
+ "PublicDescription": "l1 dcache access miss rate",
+ "BriefDescription": "l1 dcache access miss rate",
+ "MetricGroup": "Common",
+ "MetricName": "cache.l1d.rd.data.miss.rate"
+ },
+ {
+ "MetricExpr": "cache.l1d.wr.miss / cache.l1d.wr.access",
+ "PublicDescription": "l1 dcache write access miss rate",
+ "BriefDescription": "l1 dcache write access miss rate",
+ "MetricGroup": "Common",
+ "MetricName": "cache.l1d.wr.data.miss.rate"
+ },
+ {
+ "MetricExpr": "cache.l1i.rd.miss / cache.l1i.rd.access",
+ "PublicDescription": "l1 icache access miss rate",
+ "BriefDescription": "l1 icache access miss rate",
+ "MetricGroup": "Common",
+ "MetricName": "cache.l1i.rd.code.miss.rate"
+ },
+ {
+ "MetricExpr": "cache.l2.miss / cache.l2.access",
+ "PublicDescription": "l2 cache access miss rate",
+ "BriefDescription": "l2 cache access miss rate",
+ "MetricGroup": "Common",
+ "MetricName": "cache.l2.rd.miss.rate"
+ },
+ {
+ "MetricExpr": "1 - topdown.backend_bound.memory.demand_read.l3 / topdown.backend_bound.memory.demand_read",
+ "PublicDescription": "LLC access miss rate",
+ "BriefDescription": "lLC access miss rate",
+ "MetricGroup": "Common",
+ "MetricName": "cache.l3.rd.miss.rate"
+ },
+ {
+ "MetricExpr": "tlb.l1d.miss / tlb.l1d.access",
+ "PublicDescription": "L1 TLB misses caused by data loads or stores rate",
+ "BriefDescription": "L1 TLB misses caused by data loads or stores rate",
+ "MetricGroup": "Common",
+ "MetricName": "tlb.l1d.ldst.miss.rate"
+ },
+ {
+ "MetricExpr": "tlb.l1i.miss / tlb.l1i.access",
+ "PublicDescription": "L1 TLB misses caused by instruction fetch rate",
+ "BriefDescription": "L1 TLB misses caused by instruction fetch rate",
+ "MetricGroup": "Common",
+ "MetricName": "tlb.l1i.code.miss.rate"
+ },
+ {
+ "MetricExpr": " bus.rd.access / bus.access",
+ "PublicDescription": "Bus read access rate",
+ "BriefDescription": "Bus read access rate",
+ "MetricGroup": "Common",
+ "MetricName": "bus.rd.rate"
+ },
+ {
+ "MetricExpr": " bus.wr.access / bus.access",
+ "PublicDescription": "Bus write access rate",
+ "BriefDescription": "Bus write access rate",
+ "MetricGroup": "Common",
+ "MetricName": "bus.wr.rate"
+ }
+]
--
2.50.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/4] dt-bindings: vendor-prefixes: Add prefix for XuanTie
2025-11-21 6:34 ` [PATCH v2 1/4] dt-bindings: vendor-prefixes: Add prefix for XuanTie cp0613
@ 2025-11-21 8:22 ` Guo Ren
2025-11-21 9:01 ` Krzysztof Kozlowski
1 sibling, 0 replies; 13+ messages in thread
From: Guo Ren @ 2025-11-21 8:22 UTC (permalink / raw)
To: cp0613
Cc: robh, krzk+dt, conor+dt, pjw, palmer, aou, peterz, mingo, acme,
namhyung, mark.rutland, alexander.shishkin, jolsa, irogers,
adrian.hunter, james.clark, devicetree, linux-perf-users,
linux-riscv, linux-kernel
On Fri, Nov 21, 2025 at 2:35 PM <cp0613@linux.alibaba.com> wrote:
>
> From: Chen Pei <cp0613@linux.alibaba.com>
>
> Add new vendor strings to dt bindings for RISC-V vendor XuanTie.
>
> Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index f1d1882009ba..5d28b2da94cd 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -1829,6 +1829,8 @@ patternProperties:
> description: Xilinx
> "^xnano,.*":
> description: Xnano
> + "^xuantie,.*":
> + description: C-SKY Microsystems Co., Ltd. (XuanTie)
Yes, According to the "Standard Manufacturer's IDENTIFICATION CODE"
[1]. The manufacturer of Code '0x5b7' has changed from thead to
xuantie in 04/30/2024.
105 T-HEAD Semiconductor Co Ltd -> C-SKY Microsystems Co Ltd (XuanTie)
The XuanTie is the abbreviation of C-SKY Microsystems Co., Ltd, which
belongs to Alibaba Damo Academy.
[1] https://www.jedec.org/standards-documents/docs/jep-106ab
Reviewed-by: Guo Ren (Alibaba Damo Academy) <guoren@kernel.org>
Signed-off-by: Guo Ren (Alibaba Damo Academy) <guoren@kernel.org>
> "^xunlong,.*":
> description: Shenzhen Xunlong Software CO.,Limited
> "^xylon,.*":
> --
> 2.50.1
>
--
Best Regards
Guo Ren
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 2/4] dt-bindings: riscv: Add XuanTie C930 CPU compatible
2025-11-21 6:34 ` [PATCH v2 2/4] dt-bindings: riscv: Add XuanTie C930 CPU compatible cp0613
@ 2025-11-21 8:23 ` Guo Ren
2025-11-21 9:01 ` Krzysztof Kozlowski
1 sibling, 0 replies; 13+ messages in thread
From: Guo Ren @ 2025-11-21 8:23 UTC (permalink / raw)
To: cp0613
Cc: robh, krzk+dt, conor+dt, pjw, palmer, aou, peterz, mingo, acme,
namhyung, mark.rutland, alexander.shishkin, jolsa, irogers,
adrian.hunter, james.clark, devicetree, linux-perf-users,
linux-riscv, linux-kernel
On Fri, Nov 21, 2025 at 2:35 PM <cp0613@linux.alibaba.com> wrote:
>
> From: Chen Pei <cp0613@linux.alibaba.com>
>
> Update Documentation for supporting XuanTie C930.
>
> Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 153d0dac57fb..581a95eba932 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -65,6 +65,7 @@ properties:
> - thead,c908
> - thead,c910
> - thead,c920
> + - xuantie,c930
Yes, c930 belongs to XuanTie, not T-HEAD.
Reviewed-by: Guo Ren (Alibaba Damo Academy) <guoren@kernel.org>
--
Best Regards
Guo Ren
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/4] dt-bindings: vendor-prefixes: Add prefix for XuanTie
2025-11-21 6:34 ` [PATCH v2 1/4] dt-bindings: vendor-prefixes: Add prefix for XuanTie cp0613
2025-11-21 8:22 ` Guo Ren
@ 2025-11-21 9:01 ` Krzysztof Kozlowski
2025-11-21 12:30 ` Conor Dooley
1 sibling, 1 reply; 13+ messages in thread
From: Krzysztof Kozlowski @ 2025-11-21 9:01 UTC (permalink / raw)
To: cp0613
Cc: robh, krzk+dt, conor+dt, pjw, palmer, aou, peterz, mingo, acme,
namhyung, mark.rutland, alexander.shishkin, jolsa, irogers,
adrian.hunter, james.clark, guoren, devicetree, linux-perf-users,
linux-riscv, linux-kernel
On Fri, Nov 21, 2025 at 02:34:36PM +0800, cp0613@linux.alibaba.com wrote:
> From: Chen Pei <cp0613@linux.alibaba.com>
>
> Add new vendor strings to dt bindings for RISC-V vendor XuanTie.
>
> Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index f1d1882009ba..5d28b2da94cd 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -1829,6 +1829,8 @@ patternProperties:
> description: Xilinx
> "^xnano,.*":
> description: Xnano
> + "^xuantie,.*":
> + description: C-SKY Microsystems Co., Ltd. (XuanTie)
We do not create new prefixes for existing entries. You have already
csky, alibaba and thead and probably many more. Choose some appropriate.
Your commit msg should also explain anything unusual here, like above.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 2/4] dt-bindings: riscv: Add XuanTie C930 CPU compatible
2025-11-21 6:34 ` [PATCH v2 2/4] dt-bindings: riscv: Add XuanTie C930 CPU compatible cp0613
2025-11-21 8:23 ` Guo Ren
@ 2025-11-21 9:01 ` Krzysztof Kozlowski
1 sibling, 0 replies; 13+ messages in thread
From: Krzysztof Kozlowski @ 2025-11-21 9:01 UTC (permalink / raw)
To: cp0613
Cc: robh, krzk+dt, conor+dt, pjw, palmer, aou, peterz, mingo, acme,
namhyung, mark.rutland, alexander.shishkin, jolsa, irogers,
adrian.hunter, james.clark, guoren, devicetree, linux-perf-users,
linux-riscv, linux-kernel
On Fri, Nov 21, 2025 at 02:34:37PM +0800, cp0613@linux.alibaba.com wrote:
> From: Chen Pei <cp0613@linux.alibaba.com>
>
> Update Documentation for supporting XuanTie C930.
You just copied here commit subject and diff. Write something useful
instead.
>
> Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 153d0dac57fb..581a95eba932 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -65,6 +65,7 @@ properties:
> - thead,c908
> - thead,c910
> - thead,c920
> + - xuantie,c930
So that is thead...
> - const: riscv
> - items:
> - enum:
> --
> 2.50.1
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 4/4] perf vendor events riscv: Add XuanTie C930 metrics
2025-11-21 6:34 ` [PATCH v2 4/4] perf vendor events riscv: Add XuanTie C930 metrics cp0613
@ 2025-11-21 9:02 ` Krzysztof Kozlowski
0 siblings, 0 replies; 13+ messages in thread
From: Krzysztof Kozlowski @ 2025-11-21 9:02 UTC (permalink / raw)
To: cp0613
Cc: robh, krzk+dt, conor+dt, pjw, palmer, aou, peterz, mingo, acme,
namhyung, mark.rutland, alexander.shishkin, jolsa, irogers,
adrian.hunter, james.clark, guoren, devicetree, linux-perf-users,
linux-riscv, linux-kernel
On Fri, Nov 21, 2025 at 02:34:39PM +0800, cp0613@linux.alibaba.com wrote:
> From: Chen Pei <cp0613@linux.alibaba.com>
>
> This patch adds XuanTie C930 metrics, including topdown and some
Please do not use "This commit/patch/change", but imperative mood. See
longer explanation here:
https://elixir.bootlin.com/linux/v6.16/source/Documentation/process/submitting-patches.rst#L94
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/4] dt-bindings: vendor-prefixes: Add prefix for XuanTie
2025-11-21 9:01 ` Krzysztof Kozlowski
@ 2025-11-21 12:30 ` Conor Dooley
2025-11-21 13:01 ` Guo Ren
0 siblings, 1 reply; 13+ messages in thread
From: Conor Dooley @ 2025-11-21 12:30 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: cp0613, robh, krzk+dt, conor+dt, pjw, palmer, aou, peterz, mingo,
acme, namhyung, mark.rutland, alexander.shishkin, jolsa, irogers,
adrian.hunter, james.clark, guoren, devicetree, linux-perf-users,
linux-riscv, linux-kernel
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On Fri, Nov 21, 2025 at 10:01:07AM +0100, Krzysztof Kozlowski wrote:
> On Fri, Nov 21, 2025 at 02:34:36PM +0800, cp0613@linux.alibaba.com wrote:
> > From: Chen Pei <cp0613@linux.alibaba.com>
> >
> > Add new vendor strings to dt bindings for RISC-V vendor XuanTie.
> >
> > Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
> > ---
> > Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> > index f1d1882009ba..5d28b2da94cd 100644
> > --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> > +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> > @@ -1829,6 +1829,8 @@ patternProperties:
> > description: Xilinx
> > "^xnano,.*":
> > description: Xnano
> > + "^xuantie,.*":
> > + description: C-SKY Microsystems Co., Ltd. (XuanTie)
>
> We do not create new prefixes for existing entries. You have already
> csky, alibaba and thead and probably many more. Choose some appropriate.
When the vendor literally says "C-SKY", it's hard to buy why csky
shouldn't be used here. Xuantie is described as being a brand, where at
least t-head was a company. This seems akin to having
"snapdragon,msm8660" instead of "qcom,msm8660", for example.
>
> Your commit msg should also explain anything unusual here, like above.
>
> Best regards,
> Krzysztof
>
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/4] dt-bindings: vendor-prefixes: Add prefix for XuanTie
2025-11-21 12:30 ` Conor Dooley
@ 2025-11-21 13:01 ` Guo Ren
2025-11-21 17:22 ` Krzysztof Kozlowski
0 siblings, 1 reply; 13+ messages in thread
From: Guo Ren @ 2025-11-21 13:01 UTC (permalink / raw)
To: Conor Dooley
Cc: Krzysztof Kozlowski, cp0613, robh, krzk+dt, conor+dt, pjw, palmer,
aou, peterz, mingo, acme, namhyung, mark.rutland,
alexander.shishkin, jolsa, irogers, adrian.hunter, james.clark,
devicetree, linux-perf-users, linux-riscv, linux-kernel
On Fri, Nov 21, 2025 at 8:31 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Fri, Nov 21, 2025 at 10:01:07AM +0100, Krzysztof Kozlowski wrote:
> > On Fri, Nov 21, 2025 at 02:34:36PM +0800, cp0613@linux.alibaba.com wrote:
> > > From: Chen Pei <cp0613@linux.alibaba.com>
> > >
> > > Add new vendor strings to dt bindings for RISC-V vendor XuanTie.
> > >
> > > Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
> > > ---
> > > Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> > > 1 file changed, 2 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> > > index f1d1882009ba..5d28b2da94cd 100644
> > > --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> > > +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> > > @@ -1829,6 +1829,8 @@ patternProperties:
> > > description: Xilinx
> > > "^xnano,.*":
> > > description: Xnano
> > > + "^xuantie,.*":
> > > + description: C-SKY Microsystems Co., Ltd. (XuanTie)
> >
> > We do not create new prefixes for existing entries. You have already
> > csky, alibaba and thead and probably many more. Choose some appropriate.
We could leave the one C-SKY vendor entry, how about:
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -347,8 +347,8 @@ patternProperties:
description: Creative Technology Ltd
"^crystalfontz,.*":
description: Crystalfontz America, Inc.
- "^csky,.*":
- description: Hangzhou C-SKY Microsystems Co., Ltd
+ "^xuantie,.*":
+ description: C-SKY Microsystems Co., Ltd. (XuanTie)
"^csot,.*":
description: Guangzhou China Star Optoelectronics Technology Co., Ltd
"^csq,.*":
The arch/csky is the architecture name, which means "xuantie,csky".
The c810 is the CPU product name, which means "xuantie,c810" of the
"xuantie,csky" architecture.
The c930 is the CPU product name, which means "xuantie,c930".
>
> When the vendor literally says "C-SKY", it's hard to buy why csky
> shouldn't be used here. Xuantie is described as being a brand, where at
> least t-head was a company. This seems akin to having
> "snapdragon,msm8660" instead of "qcom,msm8660", for example.
Yes, XuanTie is not only a brand, but also the abbreviation of C-SKY
Microsystems Co., Ltd.
Just like:
"^100ask,.*":
description: Baiwen.com (100ask).
"^linksys,.*":
description: Belkin International, Inc. (Linksys)
>
> >
> > Your commit msg should also explain anything unusual here, like above.
> >
> > Best regards,
> > Krzysztof
> >
--
Best Regards
Guo Ren
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/4] dt-bindings: vendor-prefixes: Add prefix for XuanTie
2025-11-21 13:01 ` Guo Ren
@ 2025-11-21 17:22 ` Krzysztof Kozlowski
0 siblings, 0 replies; 13+ messages in thread
From: Krzysztof Kozlowski @ 2025-11-21 17:22 UTC (permalink / raw)
To: Guo Ren, Conor Dooley
Cc: cp0613, robh, krzk+dt, conor+dt, pjw, palmer, aou, peterz, mingo,
acme, namhyung, mark.rutland, alexander.shishkin, jolsa, irogers,
adrian.hunter, james.clark, devicetree, linux-perf-users,
linux-riscv, linux-kernel
On 21/11/2025 14:01, Guo Ren wrote:
> On Fri, Nov 21, 2025 at 8:31 PM Conor Dooley <conor@kernel.org> wrote:
>>
>> On Fri, Nov 21, 2025 at 10:01:07AM +0100, Krzysztof Kozlowski wrote:
>>> On Fri, Nov 21, 2025 at 02:34:36PM +0800, cp0613@linux.alibaba.com wrote:
>>>> From: Chen Pei <cp0613@linux.alibaba.com>
>>>>
>>>> Add new vendor strings to dt bindings for RISC-V vendor XuanTie.
>>>>
>>>> Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
>>>> ---
>>>> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
>>>> 1 file changed, 2 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
>>>> index f1d1882009ba..5d28b2da94cd 100644
>>>> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
>>>> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
>>>> @@ -1829,6 +1829,8 @@ patternProperties:
>>>> description: Xilinx
>>>> "^xnano,.*":
>>>> description: Xnano
>>>> + "^xuantie,.*":
>>>> + description: C-SKY Microsystems Co., Ltd. (XuanTie)
>>>
>>> We do not create new prefixes for existing entries. You have already
>>> csky, alibaba and thead and probably many more. Choose some appropriate.
> We could leave the one C-SKY vendor entry, how about:
>
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -347,8 +347,8 @@ patternProperties:
> description: Creative Technology Ltd
> "^crystalfontz,.*":
> description: Crystalfontz America, Inc.
> - "^csky,.*":
> - description: Hangzhou C-SKY Microsystems Co., Ltd
> + "^xuantie,.*":
> + description: C-SKY Microsystems Co., Ltd. (XuanTie)
> "^csot,.*":
> description: Guangzhou China Star Optoelectronics Technology Co., Ltd
> "^csq,.*":
>
> The arch/csky is the architecture name, which means "xuantie,csky".
>
> The c810 is the CPU product name, which means "xuantie,c810" of the
> "xuantie,csky" architecture.
>
> The c930 is the CPU product name, which means "xuantie,c930".
>
>>
>> When the vendor literally says "C-SKY", it's hard to buy why csky
>> shouldn't be used here. Xuantie is described as being a brand, where at
>> least t-head was a company. This seems akin to having
>> "snapdragon,msm8660" instead of "qcom,msm8660", for example.
> Yes, XuanTie is not only a brand, but also the abbreviation of C-SKY
> Microsystems Co., Ltd.
"XuanTie is a brand", so not suitable for vendor prefixes.
https://www.xrvm.com/declaration
What's more:
<<A reference to “C-SKY”, “we” or “us” is a reference to C-SKY
Microsystems Co., Ltd. of Room >>
So again c-sky.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2025-11-21 17:22 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
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2025-11-21 6:34 [PATCH v2 0/4] perf vendor events riscv: Add XuanTie C930 JSON files cp0613
2025-11-21 6:34 ` [PATCH v2 1/4] dt-bindings: vendor-prefixes: Add prefix for XuanTie cp0613
2025-11-21 8:22 ` Guo Ren
2025-11-21 9:01 ` Krzysztof Kozlowski
2025-11-21 12:30 ` Conor Dooley
2025-11-21 13:01 ` Guo Ren
2025-11-21 17:22 ` Krzysztof Kozlowski
2025-11-21 6:34 ` [PATCH v2 2/4] dt-bindings: riscv: Add XuanTie C930 CPU compatible cp0613
2025-11-21 8:23 ` Guo Ren
2025-11-21 9:01 ` Krzysztof Kozlowski
2025-11-21 6:34 ` [PATCH v2 3/4] perf vendor events riscv: Add XuanTie C930 JSON file cp0613
2025-11-21 6:34 ` [PATCH v2 4/4] perf vendor events riscv: Add XuanTie C930 metrics cp0613
2025-11-21 9:02 ` Krzysztof Kozlowski
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