From: Adrian Hunter <adrian.hunter@intel.com>
To: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: linux-kernel@vger.kernel.org,
"Chang S. Bae" <chang.seok.bae@intel.com>,
Masami Hiramatsu <mhiramat@kernel.org>,
Nikolay Borisov <nik.borisov@suse.com>,
Borislav Petkov <bp@alien8.de>, Ingo Molnar <mingo@redhat.com>,
"H. Peter Anvin" <hpa@zytor.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
x86@kernel.org, Jiri Olsa <jolsa@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>,
linux-perf-users@vger.kernel.org
Subject: Re: [PATCH 02/10] x86/insn: Fix PUSH instruction in x86 instruction decoder opcode map
Date: Thu, 2 May 2024 22:11:19 +0300 [thread overview]
Message-ID: <8c29642d-9e1e-46a8-83b5-03019e151807@intel.com> (raw)
In-Reply-To: <ZjOX-mE_CUOisltJ@x1>
On 2/05/24 16:41, Arnaldo Carvalho de Melo wrote:
> On Thu, May 02, 2024 at 01:58:45PM +0300, Adrian Hunter wrote:
>> The x86 instruction decoder is used not only for decoding kernel
>> instructions. It is also used by perf uprobes (user space probes) and by
>> perf tools Intel Processor Trace decoding. Consequently, it needs to
>> support instructions executed by user space also.
>
> I wonder if we should do it this way, i.e. updating both tools/ and
> kernel source code in the same patch.
>
> I think the best is to update the kernel bits, then, after that is
> merged, do the tooling part.
For objtool purposes, it might be better to do both at the same time.
>
> To avoid possible, yet unlikely, clashes in linux-next, for instance.
Always gonna find out about clashes at some point.
next prev parent reply other threads:[~2024-05-02 19:11 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-02 10:58 [PATCH 00/10] perf intel pt: Update instruction decoder for APX and other new instructions Adrian Hunter
2024-05-02 10:58 ` [PATCH 01/10] x86/insn: Add Key Locker instructions to the opcode map Adrian Hunter
2024-05-02 10:58 ` [PATCH 02/10] x86/insn: Fix PUSH instruction in x86 instruction decoder " Adrian Hunter
2024-05-02 13:41 ` Arnaldo Carvalho de Melo
2024-05-02 19:11 ` Adrian Hunter [this message]
2024-05-02 10:58 ` [PATCH 03/10] x86/insn: Add VEX versions of VPDPBUSD, VPDPBUSDS, VPDPWSSD and VPDPWSSDS Adrian Hunter
2024-05-02 10:58 ` [PATCH 04/10] x86/insn: Add misc new Intel instructions Adrian Hunter
2024-05-02 10:58 ` [PATCH 05/10] x86/insn: Add support for REX2 prefix to the instruction decoder logic Adrian Hunter
2024-05-02 18:10 ` Ian Rogers
2024-05-03 5:09 ` Adrian Hunter
2024-05-02 10:58 ` [PATCH 06/10] x86/insn: x86/insn: Add support for REX2 prefix to the instruction decoder opcode map Adrian Hunter
2024-05-02 10:58 ` [PATCH 07/10] x86/insn: Add support for APX EVEX to the instruction decoder logic Adrian Hunter
2024-05-02 10:58 ` [PATCH 08/10] x86/insn: Add support for APX EVEX instructions to the opcode map Adrian Hunter
2024-05-02 10:58 ` [PATCH 09/10] perf intel pt: Add new JMPABS instruction to the Intel PT instruction decoder Adrian Hunter
2024-05-28 18:14 ` Adrian Hunter
2024-06-18 8:05 ` Adrian Hunter
2024-05-02 10:58 ` [PATCH 10/10] perf tests: Add APX and other new instructions to x86 instruction decoder test Adrian Hunter
2024-06-26 3:59 ` (subset) [PATCH 00/10] perf intel pt: Update instruction decoder for APX and other new instructions Namhyung Kim
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