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Mon, 2 Nov 2026 10:24:05 +0000 Message-ID: <8cd3d3f3-c866-4ed3-a41f-a4210e2d73c2@intel.com> Date: Mon, 2 Nov 2026 12:23:57 +0200 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/6] perf/x86/intel/pt: Stop tracing at syscore shutdown To: Peter Zijlstra CC: Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , "Ian Rogers" , James Clark , "Thomas Gleixner" , Borislav Petkov , Dave Hansen , , "H. Peter Anvin" , "Rafael J. Wysocki" , Pavel Machek , Greg Kroah-Hartman , "Danilo Krummrich" , Johan Hovold , "Sebastian Andrzej Siewior" , Mathieu Desnoyers , Jiayuan Chen , "Steven Rostedt (Google)" , "Vineeth Pillai (Google)" , Frederic Weisbecker , "Andi Kleen" , , , , References: <20261102074039.26983-1-adrian.hunter@intel.com> <20261102074039.26983-4-adrian.hunter@intel.com> <20261102100451.GT1779021@noisy.programming.kicks-ass.net> Content-Language: en-US From: Adrian Hunter Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki In-Reply-To: <20261102100451.GT1779021@noisy.programming.kicks-ass.net> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: DUZPR01CA0146.eurprd01.prod.exchangelabs.com (2603:10a6:10:4bd::9) To IA1PR11MB7198.namprd11.prod.outlook.com (2603:10b6:208:419::15) X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA1PR11MB7198:EE_|MW3PR11MB4649:EE_ X-MS-Office365-Filtering-Correlation-Id: 6ead79b8-1fda-4a87-9c73-08df38cb6c4a X-LD-Processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|376014|7416014|1800799024|366016|4143699003|11063799006|56012099006|261028144727099003|261022105027099003|261026140227099003|261026121527099003|10067099003|22082099003|18002099003; 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>> + >> + /* >> + * After VMXON on CPUs without PT support in VMX operation, >> + * TraceEn is already clear and RTIT_CTL must not be written. >> + */ >> + rdmsrq(MSR_IA32_RTIT_CTL, ctl); >> + if (ctl & RTIT_CTL_TRACEEN) >> + wrmsrq(MSR_IA32_RTIT_CTL, ctl & ~RTIT_CTL_TRACEEN); >> +} > > Why not unconditionally do: wrmsrq(MSR_IA32_RTIT_CTL, 0), at this point? Writing 0 instead of ctl & ~RTIT_CTL_TRACEEN would be fine, but the condition is needed. The comment tries to explain. The first processor to support Intel PT (BDW) will #GP if a write is made to RTIT_CTL while VMX is on. Since VMXON clears TRACEEN, if TRACEEN is set, then the write is safe.