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([2001:660:6102:320:d6c5:cc21:7a1a:7498]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42471584306sm8662155e9.0.2024.06.18.05.49.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 18 Jun 2024 05:49:14 -0700 (PDT) Message-ID: <8d757ea3-87a3-4663-ac76-66b04e33e6b3@gmail.com> Date: Tue, 18 Jun 2024 14:49:10 +0200 Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/9] Add CPU-type to topology Content-Language: en-US To: Pawan Gupta , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: daniel.sneddon@linux.intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-perf-users@vger.kernel.org, Josh Poimboeuf , Srinivas Pandruvada , "Rafael J. Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper References: <20240617-add-cpu-type-v1-0-b88998c01e76@linux.intel.com> From: Brice Goglin In-Reply-To: <20240617-add-cpu-type-v1-0-b88998c01e76@linux.intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Le 17/06/2024 à 11:11, Pawan Gupta a écrit : > Hi, > > This series adds support for CPU-type (CPUID.1A.EAX[31-24] on Intel) to > differentiate between hybrid variants P+E, P-only, E-only that share the > same Family/Model/Stepping. One of the use case for CPU-type is the > affected CPU table for CPU vulnerabilities, which can now use the CPU-type > to filter the unaffected variants. > > * Patch 1 adds cpu-type to CPU topology structure and introduces > topology_cpu_type() to get the CPU-type. > > * Patch 2-4 replaces usages of get_this_hybrid_cpu_type() with > topology_cpu_type(). > > * Patch 5-7 Updates CPU-matching infrastructure to use CPU-type. > > * Patch 8 cleans up the affected CPU list. > > * Patch 9 uses the CPU-type to exclude P-only parts from the RFDS affected > list. Hello Is there still a plan to expose this info in sysfs? Userspace currently uses frequencies to guess which cores are E or P. Intel sent some patches several years ago [1], but they got abandoned nowhere as far as I know. There was also some discussion about using a "capacity" field like ARM does, but IIRC Intel didn't like the idea in the end. Thanks Brice [1] https://lkml.org/lkml/2020/10/2/1208