[PATCH RESEND 0/3] cstate support for CWF, LNL and PTL

[PATCH RESEND 0/3] cstate support for CWF, LNL and PTL

[Zide Chen]

This series resends three c-state patches that have been posted for a
few months but have not yet received feedback.

On behalf of Rui, I’ve included his two patches here, so that all
outstanding Intel c-state related patches can be reviewed together.

There are no code changes in this resend. Only the changelog in
[PATCH 1/3] has been updated to note that the C1E counter can only
be read via PMT.

Zhang Rui (2):
  perf/x86/intel/cstate: Remove PC3 support from LunarLake
  perf/x86/intel/cstate: Add Pantherlake support

Zide Chen (1):
  perf/x86/intel/cstate: Add Clearwater Forest support

 arch/x86/events/intel/cstate.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

-- 
2.51.1

[PATCH RESEND 1/3] perf/x86/intel/cstate: Add Clearwater Forest support

[Zide Chen]

Clearwater Forest is based on the Darkmont Atom microarchitecture.
From the perspective of C-state residency profiling, it supports the
same residency counters as Sierra Forest: CC1/CC6, PC2/PC6, and MC6.

Please note that the C1E residency counter can only be read via PMT,
not MSR. Therefore, tools relying on the perf_event framework cannot
access the C1E residency.

Cc: Artem Bityutskiy <artem.bityutskiy@intel.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw.linux@gmail.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
---
 arch/x86/events/intel/cstate.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index ec753e39b007..a5f2e0be2337 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -628,6 +628,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
 	X86_MATCH_VFM(INTEL_ATOM_GRACEMONT,	&adl_cstates),
 	X86_MATCH_VFM(INTEL_ATOM_CRESTMONT_X,	&srf_cstates),
 	X86_MATCH_VFM(INTEL_ATOM_CRESTMONT,	&grr_cstates),
+	X86_MATCH_VFM(INTEL_ATOM_DARKMONT_X,	&srf_cstates),
 
 	X86_MATCH_VFM(INTEL_ICELAKE_L,		&icl_cstates),
 	X86_MATCH_VFM(INTEL_ICELAKE,		&icl_cstates),
-- 
2.51.1

[PATCH RESEND 2/3] perf/x86/intel/cstate: Remove PC3 support from LunarLake

[Zide Chen]

From: Zhang Rui <rui.zhang@intel.com>

LunarLake doesn't support Package C3. Remove the PC3 residency counter
support from LunarLake.

Fixes: 26579860fbd5 ("perf/x86/intel/cstate: Add Lunarlake support")
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
---
 arch/x86/events/intel/cstate.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index a5f2e0be2337..2bfd011f99da 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -70,7 +70,7 @@
  *			       perf code: 0x01
  *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
  *						GLM,CNL,KBL,CML,ICL,TGL,TNT,RKL,
- *						ADL,RPL,MTL,ARL,LNL
+ *						ADL,RPL,MTL,ARL
  *			       Scope: Package (physical package)
  *	MSR_PKG_C6_RESIDENCY:  Package C6 Residency Counter.
  *			       perf code: 0x02
@@ -522,7 +522,6 @@ static const struct cstate_model lnl_cstates __initconst = {
 				  BIT(PERF_CSTATE_CORE_C7_RES),
 
 	.pkg_events		= BIT(PERF_CSTATE_PKG_C2_RES) |
-				  BIT(PERF_CSTATE_PKG_C3_RES) |
 				  BIT(PERF_CSTATE_PKG_C6_RES) |
 				  BIT(PERF_CSTATE_PKG_C10_RES),
 };
-- 
2.51.1

[PATCH RESEND 3/3] perf/x86/intel/cstate: Add Pantherlake support

[Zide Chen]

From: Zhang Rui <rui.zhang@intel.com>

Like Lunarlake, Pantherlake supports CC1/CC6/CC7 and PC2/PC6/PC10.

Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
---
 arch/x86/events/intel/cstate.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index 2bfd011f99da..fa67fda6e45b 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -41,7 +41,7 @@
  *	MSR_CORE_C1_RES: CORE C1 Residency Counter
  *			 perf code: 0x00
  *			 Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL
- *					  MTL,SRF,GRR,ARL,LNL
+ *					  MTL,SRF,GRR,ARL,LNL,PTL
  *			 Scope: Core (each processor core has a MSR)
  *	MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
  *			       perf code: 0x01
@@ -53,18 +53,19 @@
  *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
  *						SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
  *						TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
- *						GRR,ARL,LNL
+ *						GRR,ARL,LNL,PTL
  *			       Scope: Core
  *	MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
  *			       perf code: 0x03
  *			       Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,
- *						ICL,TGL,RKL,ADL,RPL,MTL,ARL,LNL
+ *						ICL,TGL,RKL,ADL,RPL,MTL,ARL,LNL,
+ *						PTL
  *			       Scope: Core
  *	MSR_PKG_C2_RESIDENCY:  Package C2 Residency Counter.
  *			       perf code: 0x00
  *			       Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
  *						KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL,
- *						RPL,SPR,MTL,ARL,LNL,SRF
+ *						RPL,SPR,MTL,ARL,LNL,SRF,PTL
  *			       Scope: Package (physical package)
  *	MSR_PKG_C3_RESIDENCY:  Package C3 Residency Counter.
  *			       perf code: 0x01
@@ -77,7 +78,7 @@
  *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
  *						SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
  *						TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
- *						ARL,LNL
+ *						ARL,LNL,PTL
  *			       Scope: Package (physical package)
  *	MSR_PKG_C7_RESIDENCY:  Package C7 Residency Counter.
  *			       perf code: 0x03
@@ -96,7 +97,7 @@
  *	MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
  *			       perf code: 0x06
  *			       Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL,
- *						TNT,RKL,ADL,RPL,MTL,ARL,LNL
+ *						TNT,RKL,ADL,RPL,MTL,ARL,LNL,PTL
  *			       Scope: Package (physical package)
  *	MSR_MODULE_C6_RES_MS:  Module C6 Residency Counter.
  *			       perf code: 0x00
@@ -652,6 +653,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
 	X86_MATCH_VFM(INTEL_ARROWLAKE_H,	&adl_cstates),
 	X86_MATCH_VFM(INTEL_ARROWLAKE_U,	&adl_cstates),
 	X86_MATCH_VFM(INTEL_LUNARLAKE_M,	&lnl_cstates),
+	X86_MATCH_VFM(INTEL_PANTHERLAKE_L,	&lnl_cstates),
 	{ },
 };
 MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
-- 
2.51.1

Re: [PATCH RESEND 0/3] cstate support for CWF, LNL and PTL

[Mi, Dapeng]

On 10/24/2025 6:37 AM, Zide Chen wrote:
> This series resends three c-state patches that have been posted for a
> few months but have not yet received feedback.
>
> On behalf of Rui, I’ve included his two patches here, so that all
> outstanding Intel c-state related patches can be reviewed together.
>
> There are no code changes in this resend. Only the changelog in
> [PATCH 1/3] has been updated to note that the C1E counter can only
> be read via PMT.
>
> Zhang Rui (2):
>   perf/x86/intel/cstate: Remove PC3 support from LunarLake
>   perf/x86/intel/cstate: Add Pantherlake support
>
> Zide Chen (1):
>   perf/x86/intel/cstate: Add Clearwater Forest support
>
>  arch/x86/events/intel/cstate.c | 18 ++++++++++--------
>  1 file changed, 10 insertions(+), 8 deletions(-)

The whole patch series looks good to me.

Reviewed-by:  Dapeng Mi <dapeng1.mi@linux.intel.com>

Re: [PATCH RESEND 1/3] perf/x86/intel/cstate: Add Clearwater Forest support

[Ingo Molnar]

* Zide Chen <zide.chen@intel.com> wrote:

> Clearwater Forest is based on the Darkmont Atom microarchitecture.
> From the perspective of C-state residency profiling, it supports the
> same residency counters as Sierra Forest: CC1/CC6, PC2/PC6, and MC6.
> 
> Please note that the C1E residency counter can only be read via PMT,
> not MSR. Therefore, tools relying on the perf_event framework cannot
> access the C1E residency.
> 
> Cc: Artem Bityutskiy <artem.bityutskiy@intel.com>
> Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
> Signed-off-by: Zhenyu Wang <zhenyuw.linux@gmail.com>
> Signed-off-by: Zide Chen <zide.chen@intel.com>

So, this is not a valid SOB chain: primary author should be the first 
SOB, or if it was co-developed, it should have the proper 
Co-developed-by tags.

Here I can see two possibilities:

(1) if Zhenyu Wang was the primary author, and Zide Chen reviewed, 
    tested and submitted it upstream, then:


  | From: Zide Chen <zide.chen@intel.com>
  | Subject: [PATCH 1/3] perf/x86/intel/cstate: Add Clearwater Forest support

    From: Zhenyu Wang <zhenyuw.linux@gmail.com>
    ...

    Signed-off-by: Zhenyu Wang <zhenyuw.linux@gmail.com>
    Signed-off-by: Zide Chen <zide.chen@intel.com>

(I.e. add the extra From line as the first line of the changelog.)

(2) if it was co-developed, with Zhenyu Wang and Zide Chen having each 
    written unique lines of code of their own that finally resulted in 
    this submission, then:

  | From: Zide Chen <zide.chen@intel.com>
  | Subject: [PATCH 1/3] perf/x86/intel/cstate: Add Clearwater Forest support

    ...

    Co-developed-by: Zide Chen <zide.chen@intel.com>
    Signed-off-by: Zide Chen <zide.chen@intel.com>
    Co-developed-by: Zhenyu Wang <zhenyuw.linux@gmail.com>
    Signed-off-by: Zhenyu Wang <zhenyuw.linux@gmail.com>

Which one was it? :-)

Thanks,

	Ingo

Re: [PATCH RESEND 1/3] perf/x86/intel/cstate: Add Clearwater Forest support

[Chen, Zide]

On 10/30/2025 2:09 AM, Ingo Molnar wrote:
> 
> * Zide Chen <zide.chen@intel.com> wrote:
> 
>> Clearwater Forest is based on the Darkmont Atom microarchitecture.
>> From the perspective of C-state residency profiling, it supports the
>> same residency counters as Sierra Forest: CC1/CC6, PC2/PC6, and MC6.
>>
>> Please note that the C1E residency counter can only be read via PMT,
>> not MSR. Therefore, tools relying on the perf_event framework cannot
>> access the C1E residency.
>>
>> Cc: Artem Bityutskiy <artem.bityutskiy@intel.com>
>> Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
>> Signed-off-by: Zhenyu Wang <zhenyuw.linux@gmail.com>
>> Signed-off-by: Zide Chen <zide.chen@intel.com>
> 
> So, this is not a valid SOB chain: primary author should be the first 
> SOB, or if it was co-developed, it should have the proper 
> Co-developed-by tags.
> 
> Here I can see two possibilities:
> 
> (1) if Zhenyu Wang was the primary author, and Zide Chen reviewed, 
>     tested and submitted it upstream, then:
> 
> 
>   | From: Zide Chen <zide.chen@intel.com>
>   | Subject: [PATCH 1/3] perf/x86/intel/cstate: Add Clearwater Forest support
> 
>     From: Zhenyu Wang <zhenyuw.linux@gmail.com>
>     ...
> 
>     Signed-off-by: Zhenyu Wang <zhenyuw.linux@gmail.com>
>     Signed-off-by: Zide Chen <zide.chen@intel.com>
> 
> (I.e. add the extra From line as the first line of the changelog.)

Yes, that is the case.
Thank you very much for pointing this out! I will pay extra attention to
the SoB chain going forward.


> (2) if it was co-developed, with Zhenyu Wang and Zide Chen having each 
>     written unique lines of code of their own that finally resulted in 
>     this submission, then:
> 
>   | From: Zide Chen <zide.chen@intel.com>
>   | Subject: [PATCH 1/3] perf/x86/intel/cstate: Add Clearwater Forest support
> 
>     ...
> 
>     Co-developed-by: Zide Chen <zide.chen@intel.com>
>     Signed-off-by: Zide Chen <zide.chen@intel.com>
>     Co-developed-by: Zhenyu Wang <zhenyuw.linux@gmail.com>
>     Signed-off-by: Zhenyu Wang <zhenyuw.linux@gmail.com>
> 
> Which one was it? :-)
> 
> Thanks,
> 
> 	Ingo