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b=h+9dgI6FcdQq7SEY9KsJ+vUOENDpOuRA0x0OOn5BdKaUld2ZHub67SpOikawHwHRgWmiW3BnKGyIj155jX1mRYaK0/n+cXPeOTe80h6UYcvZ/i4xVBJxXklEZINx6xjUnc5crfMp2FqIKeTXeMAJ18NaWsEOcIlXoTe/mhMF5wM= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from BN8PR12MB3505.namprd12.prod.outlook.com (2603:10b6:408:69::17) by BN6PR1201MB2497.namprd12.prod.outlook.com (2603:10b6:404:b3::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.20; Mon, 22 Nov 2021 16:51:48 +0000 Received: from BN8PR12MB3505.namprd12.prod.outlook.com ([fe80::704c:60ed:36f:4e4c]) by BN8PR12MB3505.namprd12.prod.outlook.com ([fe80::704c:60ed:36f:4e4c%7]) with mapi id 15.20.4713.024; Mon, 22 Nov 2021 16:51:48 +0000 Message-ID: <8fde297d-880f-c13d-b42c-be9f554ccb20@amd.com> Date: Mon, 22 Nov 2021 10:51:44 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.3.1 Subject: Re: [PATCH 1/2] perf/docs: Add info on AMD raw event encoding Content-Language: en-US To: Sandipan Das , acme@kernel.org Cc: santosh.shukla@amd.com, ravi.bangoria@amd.com, ananth.narayan@amd.com, rrichter@amd.com, linux-perf-users@vger.kernel.org, jolsa@redhat.com, kjain@linux.ibm.com References: <20211119111234.170726-1-sandipan.das@amd.com> From: Kim Phillips In-Reply-To: <20211119111234.170726-1-sandipan.das@amd.com> Content-Type: text/plain; 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BTW, "Zen" is a broad term to describe the new generation of core microarchitectures. "Family" in x86 speak usually refers to a number, as in the Family, Model, and Stepping number triplet. > select codes and unit masks larger than a byte. The core > PMU, for example, uses 12-bit event select codes split > between bits 0-7 and 32-35 of the PERF_CTL MSRs as can > be seen from /sys/bus/event_sources/devices/cpu/format/*. > > The Processor Programming Reference (PPR) lists the event > codes as unified 12-bit hexadecimal values instead and the > split between the bits is not apparent to someone who is > not aware of the layout of the PERF_CTL MSRs. > > 8-bit event select codes continue to work as the layout > matches that of the PERF_CTL MSRs i.e. bits 0-7 for event > select and 8-15 for unit mask. > > This adds details in the perf man pages about using > /sys/bus/event_sources/devices/*/format/* for determining > the correct raw event encoding scheme. > > E.g. the "ic_tag_hit_miss.all_instruction_cache_accesses" > event with code 0x18e and umask 0x1f can be programmed > using its symbolic name as: > > $ sudo perf --debug perf-event-open stat -e ic_tag_hit_miss.all_instruction_cache_accesses sleep 1 > ------------------------------------------------------------ > perf_event_attr: > type 4 > size 128 > config 0x100001f8e > sample_type IDENTIFIER > read_format TOTAL_TIME_ENABLED|TOTAL_TIME_RUNNING > disabled 1 > inherit 1 > enable_on_exec 1 > exclude_guest 1 > ------------------------------------------------------------ > [...] > > In raw format, it may be programmed incorrectly as: > > $ sudo perf --debug perf-event-open stat -e r1f18e sleep 1 > ------------------------------------------------------------ > perf_event_attr: > type 4 > size 128 > config 0x1f18e > sample_type IDENTIFIER > read_format TOTAL_TIME_ENABLED|TOTAL_TIME_RUNNING > disabled 1 > inherit 1 > enable_on_exec 1 > exclude_guest 1 > ------------------------------------------------------------ > [...] > > When it should have been based on the format from sysfs: > > $ cat /sys/bus/event_source/devices/cpu/format/event > config:0-7,32-35 > > $ sudo perf --debug perf-event-open stat -e r100001f8e sleep 1 > ------------------------------------------------------------ > perf_event_attr: > type 4 > size 128 > config 0x100001f8e > sample_type IDENTIFIER > read_format TOTAL_TIME_ENABLED|TOTAL_TIME_RUNNING > disabled 1 > inherit 1 > enable_on_exec 1 > exclude_guest 1 > ------------------------------------------------------------ > [...] > > Signed-off-by: Sandipan Das > --- > tools/perf/Documentation/perf-list.txt | 36 +++++++++++++++++++++++- > tools/perf/Documentation/perf-record.txt | 6 ++-- > tools/perf/Documentation/perf-stat.txt | 6 ++-- > tools/perf/Documentation/perf-top.txt | 7 +++-- > 4 files changed, 47 insertions(+), 8 deletions(-) > > diff --git a/tools/perf/Documentation/perf-list.txt b/tools/perf/Documentation/perf-list.txt > index 4dc8d0af19df..9c54c0566fda 100644 > --- a/tools/perf/Documentation/perf-list.txt > +++ b/tools/perf/Documentation/perf-list.txt > @@ -94,7 +94,7 @@ RAW HARDWARE EVENT DESCRIPTOR > Even when an event is not available in a symbolic form within perf right now, > it can be encoded in a per processor specific way. > > -For instance For x86 CPUs NNN represents the raw register encoding with the > +For instance on x86 CPUs, N is a hexadecimal value that represents the raw register encoding with the > layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout > of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344, > Figure 13-7 Performance Event-Select Register (PerfEvtSeln)). > @@ -126,6 +126,40 @@ It's also possible to use pmu syntax: > perf record -e cpu/r1a8/ ... > perf record -e cpu/r0x1a8/ ... > > +Some processors, like those from the AMD Zen family, support event codes and > +unit masks larger than a byte. In such cases, the bits corresponding to the > +event configuration parameters can be seen with: > + > + cat /sys/bus/event_source/devices//format/ > + > +Example: > + > +If the AMD docs for an EPYC 7713 processor describe an event as: > + > + Event Umask Event Mask > + Num. Value Mnemonic Description Comment > + > + 18EH 1FH ic_tag_hit_miss.all_instruction_cache_accesses Counts various Use umask=1f to count > + IC tag related all instruction cache > + hit and miss accesses > + events > + > +raw encoding of 0x1F18E cannot be used since the upper nibble of the > +EventSelect bits have to be specified via bits 32-35 as can be seen with: > + > + cat /sys/bus/event_source/devices/cpu/format/event > + > +raw encoding of 0x100001F8E should be used instead: > + > + perf stat -e r100001f8e -a sleep 1 > + perf record -e r100001f8e ... Would it be better to have an example where the most significant hex digit of the unit mask were different from that of the triple- digit event, so people's eyes could easily see where each go? I'm talking about those two '1's.. > +It's also possible to use pmu syntax: > + > + perf record -e r100001f8e -a sleep 1 > + perf record -e cpu/r100001f8e/ ... > + perf record -e cpu/r0x100001f8e/ ... > + > You should refer to the processor specific documentation for getting these > details. Some of them are referenced in the SEE ALSO section below. > > diff --git a/tools/perf/Documentation/perf-record.txt b/tools/perf/Documentation/perf-record.txt > index 3cf7bac67239..43d945e12d97 100644 > --- a/tools/perf/Documentation/perf-record.txt > +++ b/tools/perf/Documentation/perf-record.txt > @@ -30,8 +30,10 @@ OPTIONS > > - a symbolic event name (use 'perf list' to list all events) > > - - a raw PMU event (eventsel+umask) in the form of rNNN where NNN is a > - hexadecimal event descriptor. > + - a raw PMU event in the form of rN where N is a hexadecimal value > + that represents the raw register encoding with the layout of the > + event control registers as described by entries in > + /sys/bus/event_sources/devices//format/*. r notation is for the cpu pmu only. > > - a symbolic or raw PMU event followed by an optional colon > and a list of event modifiers, e.g., cpu-cycles:p. See the > diff --git a/tools/perf/Documentation/perf-stat.txt b/tools/perf/Documentation/perf-stat.txt > index 7e6fb7cbc0f4..0f279b5498e4 100644 > --- a/tools/perf/Documentation/perf-stat.txt > +++ b/tools/perf/Documentation/perf-stat.txt > @@ -36,8 +36,10 @@ report:: > > - a symbolic event name (use 'perf list' to list all events) > > - - a raw PMU event (eventsel+umask) in the form of rNNN where NNN is a > - hexadecimal event descriptor. > + - a raw PMU event in the form of rN where N is a hexadecimal value > + that represents the raw register encoding with the layout of the > + event control registers as described by entries in > + /sys/bus/event_sources/devices//format/*. same here. > - a symbolic or raw PMU event followed by an optional colon > and a list of event modifiers, e.g., cpu-cycles:p. See the > diff --git a/tools/perf/Documentation/perf-top.txt b/tools/perf/Documentation/perf-top.txt > index 9898a32b8d9c..21028910561f 100644 > --- a/tools/perf/Documentation/perf-top.txt > +++ b/tools/perf/Documentation/perf-top.txt > @@ -38,9 +38,10 @@ Default is to monitor all CPUS. > -e :: > --event=:: > Select the PMU event. Selection can be a symbolic event name > - (use 'perf list' to list all events) or a raw PMU > - event (eventsel+umask) in the form of rNNN where NNN is a > - hexadecimal event descriptor. > + (use 'perf list' to list all events) or a raw PMU event in the form > + of rN where N is a hexadecimal value that represents the raw register > + encoding with the layout of the event control registers as described > + by entries in /sys/bus/event_sources/devices//format/*. and here. Thanks, Kim