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Peter Anvin" , Andrii Nakryiko , Song Liu , Ravi Bangoria , Ananth Narayan References: <20261007181002.4005262-1-sandipan.das@amd.com> <20261012153014.GU4121339@noisy.programming.kicks-ass.net> Content-Language: en-US From: Sandipan Das In-Reply-To: <20261012153014.GU4121339@noisy.programming.kicks-ass.net> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-ClientProxiedBy: PNYPR01CA0078.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:2b4::9) To PH7PR12MB5712.namprd12.prod.outlook.com (2603:10b6:510:1e3::13) Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH7PR12MB5712:EE_|MN2PR12MB4453:EE_ X-MS-Office365-Filtering-Correlation-Id: c22643f1-b3fb-4fc7-cfb4-08df28f585aa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|1800799024|23010399003|56012099006|4143699003|261009223027099003|11063799006|10067099003|18002099003|22082099003; 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The entries past lbr_stack.nr are >> invalid, but they end up reaching BPF programs. >> >> Limit copying to lbr_stack.nr entries and also reset lbr_stack.nr when >> amd_pmu_lbr_read() skips reading the registers, so that a stale count >> is never reused. >> >> Fixes: a4d18112e531 ("perf/x86/amd: Support capturing LBR from software events") >> Reported-by: Sashiko >> Closes: https://lore.kernel.org/all/sashiko-outbox-163130@kernel.org/ >> Signed-off-by: Sandipan Das >> --- >> arch/x86/events/amd/core.c | 2 +- >> arch/x86/events/amd/lbr.c | 4 +++- >> 2 files changed, 4 insertions(+), 2 deletions(-) >> >> diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c >> index 49b6b8fce566..bf631f60757c 100644 >> --- a/arch/x86/events/amd/core.c >> +++ b/arch/x86/events/amd/core.c >> @@ -944,7 +944,7 @@ static int amd_pmu_v2_snapshot_branch_stack(struct perf_branch_entry *entries, u >> cpuc = this_cpu_ptr(&cpu_hw_events); >> >> amd_pmu_lbr_read(); >> - cnt = min(cnt, x86_pmu.lbr_nr); >> + cnt = min(cnt, cpuc->lbr_stack.nr); >> memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt); >> >> amd_pmu_v2_enable_all(0); >> diff --git a/arch/x86/events/amd/lbr.c b/arch/x86/events/amd/lbr.c >> index 1e1b2f08cb51..a00d3850c4a8 100644 >> --- a/arch/x86/events/amd/lbr.c >> +++ b/arch/x86/events/amd/lbr.c >> @@ -165,8 +165,10 @@ void amd_pmu_lbr_read(void) >> struct branch_entry entry; >> int out = 0, idx, i; >> >> - if (!cpuc->lbr_users) >> + if (!cpuc->lbr_users) { >> + cpuc->lbr_stack.nr = 0; >> return; >> + } >> >> for (i = 0; i < x86_pmu.lbr_nr; i++) { >> entry.from.full = amd_pmu_lbr_get_from(i); > > You now seem to deviate from what the Intel code does. Please clarify. Yes, it is a deviation. I thought of proposing the following but didn't proceed because I was not sure about the if condition in the second hunk which considers things other than cpuc->lbr_users for an early return. diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 0a34d674df59..5dfb9e9156e8 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -2822,7 +2822,7 @@ __intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); intel_pmu_lbr_read(); - cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr); + cnt = min_t(unsigned int, cnt, cpuc->lbr_stack.nr); memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt); intel_pmu_enable_all(0); diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c index 0b446d8912e4..6b070490f461 100644 --- a/arch/x86/events/intel/lbr.c +++ b/arch/x86/events/intel/lbr.c @@ -1026,8 +1026,10 @@ void intel_pmu_lbr_read(void) * but this simple approach seems to work for now. */ if (!cpuc->lbr_users || vlbr_exclude_host() || - cpuc->lbr_users == cpuc->lbr_pebs_users) + cpuc->lbr_users == cpuc->lbr_pebs_users) { + cpuc->lbr_stack.nr = 0; return; + } x86_pmu.lbr_read(cpuc);