From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 403F3C433EF for ; Wed, 8 Jun 2022 10:46:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237233AbiFHKqE (ORCPT ); Wed, 8 Jun 2022 06:46:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59064 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237155AbiFHKqC (ORCPT ); Wed, 8 Jun 2022 06:46:02 -0400 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC61A10D5C3; Wed, 8 Jun 2022 03:45:58 -0700 (PDT) Received: from fraeml712-chm.china.huawei.com (unknown [172.18.147.206]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4LJ3hH55gqz67jfG; Wed, 8 Jun 2022 18:42:23 +0800 (CST) Received: from lhreml724-chm.china.huawei.com (10.201.108.75) by fraeml712-chm.china.huawei.com (10.206.15.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Wed, 8 Jun 2022 12:45:56 +0200 Received: from [10.47.90.54] (10.47.90.54) by lhreml724-chm.china.huawei.com (10.201.108.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Wed, 8 Jun 2022 11:45:55 +0100 Message-ID: <9e981523-6032-fd24-08f9-0ef771cd1c2e@huawei.com> Date: Wed, 8 Jun 2022 11:45:53 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: Re: [PATCH v3 3/4] RISC-V: Added generic pmu-events mapfile To: Nikita Shubin CC: Genevieve Chan , =?UTF-8?B?Sm/Do28gTcOhcmlvIERvbWluZ29z?= , Nikita Shubin , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , "Namhyung Kim" , Paul Walmsley , "Palmer Dabbelt" , Albert Ou , open list , "open list:PERFORMANCE EVENTS SUBSYSTEM" , "open list:RISC-V ARCHITECTURE" References: <20220607131648.29439-1-nikita.shubin@maquefel.me> <20220607131648.29439-4-nikita.shubin@maquefel.me> From: John Garry In-Reply-To: <20220607131648.29439-4-nikita.shubin@maquefel.me> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.47.90.54] X-ClientProxiedBy: lhreml744-chm.china.huawei.com (10.201.108.194) To lhreml724-chm.china.huawei.com (10.201.108.75) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-perf-users@vger.kernel.org On 07/06/2022 14:16, Nikita Shubin wrote: > From: João Mário Domingos > > The pmu-events now supports custom events for RISC-V, plus the cycle, > time and instret events were defined. > > Signed-off-by: João Mário Domingos > Tested-by: Nikita Shubin > --- > tools/perf/pmu-events/arch/riscv/mapfile.csv | 14 +++++++++++++ > .../pmu-events/arch/riscv/riscv-generic.json | 20 +++++++++++++++++++ > 2 files changed, 34 insertions(+) > create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv > create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-generic.json > > diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv > new file mode 100644 > index 000000000000..4f2aa199d9cb > --- /dev/null > +++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv > @@ -0,0 +1,14 @@ > +# Format: > +# MIDR,Version,JSON/file/pathname,Type > +# > +# where > +# MIDR Processor version ARM, no? > +# Variant[23:20] and Revision [3:0] should be zero. > +# Version could be used to track version of JSON file > +# but currently unused. > +# JSON/file/pathname is the path to JSON file, relative > +# to tools/perf/pmu-events/arch/riscv/. > +# Type is core, uncore etc > +# > +# > +#Family-model,Version,Filename,EventType > diff --git a/tools/perf/pmu-events/arch/riscv/riscv-generic.json b/tools/perf/pmu-events/arch/riscv/riscv-generic.json > new file mode 100644 > index 000000000000..013e50efad99 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/riscv/riscv-generic.json where or how are these referenced? > @@ -0,0 +1,20 @@ > +[ > + { > + "PublicDescription": "CPU Cycles", > + "EventCode": "0x00", > + "EventName": "riscv_cycles", > + "BriefDescription": "CPU cycles RISC-V generic counter" > + }, > + { > + "PublicDescription": "CPU Time", > + "EventCode": "0x01", > + "EventName": "riscv_time", > + "BriefDescription": "CPU time RISC-V generic counter" > + }, > + { > + "PublicDescription": "CPU Instructions", > + "EventCode": "0x02", > + "EventName": "riscv_instret", > + "BriefDescription": "CPU retired instructions RISC-V generic counter" > + } > +] > \ No newline at end of file