messages from 2026-06-09 06:01:58 to 2026-06-09 10:05:03 UTC [more...]
[Patch v2 4/9] perf/x86/intel: Fallback to sw branch type decoding if no hw decoding
2026-06-09 10:04 UTC (3+ messages)
[Patch v2 9/9] perf/core: Check kernel access when kernel callchains are requested
2026-06-09 9:49 UTC (3+ messages)
[Patch v2 6/9] perf/x86/intel: Validate return value of intel_pmu_init_hybrid()
2026-06-09 9:44 UTC (3+ messages)
[Patch v2 5/9] perf/x86/intel: Drop LBR entries whose privilege level mismatches br_sel
2026-06-09 9:40 UTC (3+ messages)
[PATCH v2 0/8] riscv: Add reliable stack unwinding for livepatch
2026-06-09 8:44 UTC (14+ messages)
` [PATCH v3 "
` [PATCH v3 1/8] scripts/sorttable: Handle RISC-V patchable ftrace entries
` [PATCH v3 2/8] riscv: stacktrace: Add frame record metadata
` [PATCH v3 3/8] riscv: stacktrace: disable KASAN and KCOV instrumentation for stacktrace.o
` [PATCH v3 4/8] riscv: ftrace: always preserve s0 in dynamic ftrace register frame
` [PATCH v3 5/8] riscv: stacktrace: introduce stack-bound tracking helpers
` [PATCH v3 6/8] riscv: stacktrace: switch to frame-pointer based unwinder
` [PATCH v3 7/8] riscv: Kconfig: enable HAVE_RELIABLE_STACKTRACE and HAVE_LIVEPATCH
` [PATCH v3 8/8] selftests/livepatch: Add RISC-V syscall wrapper prefix
[PATCH v2 0/2] perf: riscv: fix register name strings
2026-06-09 8:13 UTC (3+ messages)
` [PATCH v2 1/2] perf: avoid redefinition warnings for REG_DWARFNUM_NAME
` [PATCH v2 2/2] perf riscv: fix register name strings
[PATCH] tools/perf/sched: Update process names of processes in zombie state for both -s and -S options
2026-06-09 8:12 UTC (8+ messages)
[PATCH] perf riscv: fix register name strings
2026-06-09 7:32 UTC (5+ messages)
[PATCH v2 0/7] perf annotate: Add elfutils libasm disassembler support
2026-06-09 7:22 UTC (13+ messages)
` [PATCH v2 1/7] tools build: Add feature check for elfutils libasm
` [PATCH v2 2/7] perf build: Add build support and capability "
` [PATCH v2 3/7] perf annotate: Implement elfutils libasm disassembler backend
` [PATCH v2 4/7] perf annotate: Add --disassembler command-line option
` [PATCH v2 5/7] perf test: Enhance annotate test coverage and isolate config
` [PATCH v2 6/7] perf annotate: Support BPF JIT disassembly via genelf
` [PATCH v2 7/7] perf test: Add BPF JIT annotation test coverage for all disassemblers
[PATCH v1 0/3] perf pmu: Add tool-provided NVMe PMU
2026-06-09 7:21 UTC (6+ messages)
` [PATCH v1 1/3] perf build: Add libnvme feature detection
` [PATCH v1 2/3] perf pmu: Implement tool-provided NVMe PMU
` [PATCH v1 3/3] perf tests: Add NVMe PMU event parsing test
[PATCH 0/3] perf: marvell: LLC-TAD PMU MPAM filtering and CN20K support
2026-06-09 6:36 UTC (4+ messages)
` [PATCH 3/3] dt-bindings: perf: marvell: Extend CN10K TAD PMU binding for CN20K
` [EXTERNAL] "
[PATCH v6 00/21] Add Counter delegation ISA extension support
2026-06-09 6:33 UTC (31+ messages)
` [PATCH v6 06/21] dt-bindings: riscv: add Smcntrpmf ISA extension description
` [PATCH v6 07/21] RISC-V: Add Sscfg extension CSR definition
` [PATCH v6 08/21] RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing
` [PATCH v6 09/21] dt-bindings: riscv: add Counter delegation ISA extensions description
` [PATCH v6 10/21] RISC-V: perf: Restructure the SBI PMU code
` [PATCH v6 11/21] RISC-V: perf: Modify the counter discovery mechanism
` [PATCH v6 12/21] RISC-V: perf: Add a mechanism to defined legacy event encoding
` [PATCH v6 13/21] RISC-V: perf: Implement supervisor counter delegation support
` [PATCH v6 14/21] RISC-V: perf: Skip PMU SBI extension when not implemented
` [PATCH v6 15/21] RISC-V: perf: Use config2/vendor table for event to counter mapping
` [PATCH v6 16/21] RISC-V: perf: Add legacy event encodings via sysfs
` [PATCH v6 17/21] RISC-V: perf: Add Qemu virt machine events
` [PATCH v6 18/21] tools/perf: Support event code for arch standard events
` [PATCH v6 19/21] tools/perf: Add RISC-V CounterIDMask event field
` [PATCH v6 20/21] TEST(do-not-upstream): fake qemu-virt PMU events for cdeleg counter-mask testing
` [PATCH v6 21/21] TEST(do-not-upstream): fake qemu vendor JSON + mapfile entry for CounterIDMask path
[PATCH v6 04/21] RISC-V: Define indirect CSR access helpers
2026-06-09 6:15 UTC (2+ messages)
[PATCH v6 03/21] dt-bindings: riscv: add Sxcsrind ISA extension description
2026-06-09 6:09 UTC (2+ messages)
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