messages from 2026-06-19 16:06:06 to 2026-06-20 23:25:24 UTC [more...]
[PATCH v6 13/21] RISC-V: perf: Implement supervisor counter delegation support
2026-06-20 23:25 UTC (3+ messages)
[PATCH v6 14/21] RISC-V: perf: Skip PMU SBI extension when not implemented
2026-06-20 23:15 UTC (3+ messages)
[PATCH v6 17/21] RISC-V: perf: Add Qemu virt machine events
2026-06-20 0:37 UTC (3+ messages)
[PATCH v6 16/21] RISC-V: perf: Add legacy event encodings via sysfs
2026-06-20 0:35 UTC (3+ messages)
[PATCH v6 11/21] RISC-V: perf: Modify the counter discovery mechanism
2026-06-20 0:31 UTC (3+ messages)
[PATCH v6 10/21] RISC-V: perf: Restructure the SBI PMU code
2026-06-20 0:17 UTC (3+ messages)
[PATCH v6 21/21] TEST(do-not-upstream): fake qemu vendor JSON + mapfile entry for CounterIDMask path
2026-06-20 0:04 UTC (3+ messages)
[PATCH v6 09/21] dt-bindings: riscv: add Counter delegation ISA extensions description
2026-06-19 23:49 UTC (3+ messages)
[PATCH v6 08/21] RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing
2026-06-19 23:44 UTC (3+ messages)
[PATCH v6 06/21] dt-bindings: riscv: add Smcntrpmf ISA extension description
2026-06-19 23:40 UTC (3+ messages)
[PATCH v6 03/21] dt-bindings: riscv: add Sxcsrind ISA extension description
2026-06-19 23:39 UTC (3+ messages)
[PATCH v6 04/21] RISC-V: Define indirect CSR access helpers
2026-06-19 23:39 UTC (3+ messages)
[PATCH v2] arm64/hw_breakpoint: reject unaligned watchpoints that would truncate BAS
2026-06-19 16:36 UTC (2+ messages)
[PATCH v2 0/2] RISC-V IOMMU HPM support
2026-06-19 16:05 UTC (3+ messages)
` [PATCH v2 1/2] drivers/perf: riscv-iommu: add risc-v iommu pmu driver
page: | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox