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From: Joel Stanley <joel@jms.id.au>
To: Jesse Taube <jesse@rivosinc.com>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	 linux-perf-users@vger.kernel.org,
	linux-kselftest@vger.kernel.org
Subject: Re: [PATCH 8/8] selftests: riscv: Add test for hardware breakpoints
Date: Fri, 15 Aug 2025 15:42:16 +1000	[thread overview]
Message-ID: <CACPK8Xd2QfL460LY2T0ia7Akb79fEXKF2+=B27M8q5j7jUoouQ@mail.gmail.com> (raw)
In-Reply-To: <20250805193955.798277-9-jesse@rivosinc.com>

Hi Jesse,

We had a pretty huge cc list on the thread, I've trimmed it right
back. Feel free to add some people back but keep it focused.

On Wed, 6 Aug 2025 at 05:42, Jesse Taube <jesse@rivosinc.com> wrote:
>
> Add riscv specific selftest for hardhardware breakpoints.

nit: double hardware

> These tests are based on:
> tools/testing/selftests/breakpoints/breakpoint_test_arm64.c

The sefltest didn't build for me. There's a few suggested fixes below.

> Signed-off-by: Jesse Taube <jesse@rivosinc.com>
> ---
> The selftest fails as register_user_hw_breakpoint seemingly does not
> call arch_install_hw_breakpoint. The test also seems to fail on arm64
> in the same way when I tested it.

Is this still a problem with your patchset?

Do you test in qemu? Can you share your version, command line, etc?

> --- /dev/null
> +++ b/tools/testing/selftests/riscv/breakpoints/Makefile
> @@ -0,0 +1,12 @@
> +# SPDX-License-Identifier: GPL-2.0
> +# Copyright (C) 2021 ARM Limited
> +# Originally tools/testing/arm64/abi/Makefile

CFLAGS += $(KHDR_INCLUDES)

This adds -isystem to include local headers for the up to date
ptrace.h and elf.h definitions.

 $ make headers
 $ make -C tools/testing/selftests CROSS_COMPILE=riscv64-linux-gnu-
ARCH=riscv TARGETS=riscv/breakpoints
     make: Entering directory 'tools/testing/selftests'
     riscv64-linux-gnu-gcc -static
-otools/testing/selftests/riscv/breakpoints/breakpoint_test
     -isystem usr/include -Itools/testing/selftests/../../../tools/include
     -D_GNU_SOURCE=   breakpoint_test.c

> +
> +CFLAGS += -I$(top_srcdir)/tools/include
> +
> +TEST_GEN_PROGS := breakpoint_test
> +
> +include ../../lib.mk
> +
> +$(OUTPUT)/breakpoint_test: breakpoint_test.c
> +       $(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^
> diff --git a/tools/testing/selftests/riscv/breakpoints/breakpoint_test.c b/tools/testing/selftests/riscv/breakpoints/breakpoint_test.c
> new file mode 100644
> index 000000000000..faeecc72da12
> --- /dev/null
> +++ b/tools/testing/selftests/riscv/breakpoints/breakpoint_test.c
> @@ -0,0 +1,246 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2016 Google, Inc.
> + *
> + * Original Code by Pavel Labath <labath@google.com>
> + *
> + * Code modified by Pratyush Anand <panand@redhat.com>
> + * for testing different byte select for each access size.
> + * Originally tools/testing/selftests/breakpoints/breakpoint_test_arm64.c
> + */
> +
> +#define _GNU_SOURCE
> +
> +#include <asm/ptrace.h>
> +#include <sys/types.h>
> +#include <sys/wait.h>
> +#include <sys/ptrace.h>
> +#include <sys/param.h>
> +#include <sys/uio.h>
> +#include <stdint.h>
> +#include <stdbool.h>
> +#include <stddef.h>
> +#include <string.h>
> +#include <stdio.h>
> +#include <unistd.h>
> +#include <elf.h>

This is the wrong elf.h, we want the one with NT_RISCV_HW_BREAK.

-#include <elf.h>
+#include <linux/elf.h>


> +#include <errno.h>
> +#include <signal.h>
> +
> +#include "../../kselftest.h"
> +
> +#define MAX_BP_SIZE 8
> +

  reply	other threads:[~2025-08-15  5:42 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-05 19:39 [PATCH 0/8] riscv: add initial support for hardware breakpoints Jesse Taube
2025-08-05 19:39 ` [PATCH 1/8] riscv: Add insn.c, consolidate instruction decoding Jesse Taube
2025-08-05 19:39 ` [PATCH 2/8] riscv: Add SBI debug trigger extension and function ids Jesse Taube
2025-08-05 19:39 ` [PATCH 3/8] riscv: insn: Add get_insn_nofault Jesse Taube
2025-08-05 19:39 ` [PATCH 4/8] riscv: Introduce support for hardware break/watchpoints Jesse Taube
2025-08-05 19:39 ` [PATCH 5/8] riscv: hw_breakpoint: Use icount for single stepping Jesse Taube
2025-08-11  9:41   ` Anup Patel
2025-08-05 19:39 ` [PATCH 6/8] riscv: ptrace: Add hw breakpoint support Jesse Taube
2025-08-05 19:39 ` [PATCH 7/8] riscv: ptrace: Add hw breakpoint regset Jesse Taube
2025-08-05 19:39 ` [PATCH 8/8] selftests: riscv: Add test for hardware breakpoints Jesse Taube
2025-08-15  5:42   ` Joel Stanley [this message]
2025-08-22 17:58     ` Jesse Taube
  -- strict thread matches above, loose matches on Subject: below --
2025-08-22 17:47 [PATCH 0/8] riscv: add initial support " Jesse Taube
2025-08-22 17:47 ` [PATCH 8/8] selftests: riscv: Add test " Jesse Taube

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