From: Mike Leach <mike.leach@linaro.org>
To: James Clark <james.clark@arm.com>
Cc: linux-perf-users@vger.kernel.org,
gankulkarni@os.amperecomputing.com,
scclevenger@os.amperecomputing.com, coresight@lists.linaro.org,
suzuki.poulose@arm.com,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Jiri Olsa <jolsa@kernel.org>, Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
John Garry <john.g.garry@oracle.com>,
Will Deacon <will@kernel.org>, Leo Yan <leo.yan@linux.dev>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com
Subject: Re: [PATCH 10/17] coresight: Move struct coresight_trace_id_map to common header
Date: Wed, 1 May 2024 12:11:21 +0100 [thread overview]
Message-ID: <CAJ9a7VghkeaJ8e-mEZKodicQ++QyW_SKfacsPPsfQb2PiT6H0w@mail.gmail.com> (raw)
In-Reply-To: <20240429152207.479221-11-james.clark@arm.com>
On Mon, 29 Apr 2024 at 16:24, James Clark <james.clark@arm.com> wrote:
>
> The trace ID maps will need to be created and stored by the core and
> Perf code so move the definition up to the common header.
>
> Signed-off-by: James Clark <james.clark@arm.com>
> ---
> .../hwtracing/coresight/coresight-trace-id.c | 1 +
> .../hwtracing/coresight/coresight-trace-id.h | 19 -------------------
> include/linux/coresight.h | 18 ++++++++++++++++++
> 3 files changed, 19 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-trace-id.c b/drivers/hwtracing/coresight/coresight-trace-id.c
> index af5b4ef59cea..19005b5b4dc4 100644
> --- a/drivers/hwtracing/coresight/coresight-trace-id.c
> +++ b/drivers/hwtracing/coresight/coresight-trace-id.c
> @@ -3,6 +3,7 @@
> * Copyright (c) 2022, Linaro Limited, All rights reserved.
> * Author: Mike Leach <mike.leach@linaro.org>
> */
> +#include <linux/coresight.h>
> #include <linux/coresight-pmu.h>
> #include <linux/cpumask.h>
> #include <linux/kernel.h>
> diff --git a/drivers/hwtracing/coresight/coresight-trace-id.h b/drivers/hwtracing/coresight/coresight-trace-id.h
> index 3797777d367e..49438a96fcc6 100644
> --- a/drivers/hwtracing/coresight/coresight-trace-id.h
> +++ b/drivers/hwtracing/coresight/coresight-trace-id.h
> @@ -32,10 +32,6 @@
> #include <linux/bitops.h>
> #include <linux/types.h>
>
> -
> -/* architecturally we have 128 IDs some of which are reserved */
> -#define CORESIGHT_TRACE_IDS_MAX 128
> -
> /* ID 0 is reserved */
> #define CORESIGHT_TRACE_ID_RES_0 0
>
> @@ -46,21 +42,6 @@
> #define IS_VALID_CS_TRACE_ID(id) \
> ((id > CORESIGHT_TRACE_ID_RES_0) && (id < CORESIGHT_TRACE_ID_RES_TOP))
>
> -/**
> - * Trace ID map.
> - *
> - * @used_ids: Bitmap to register available (bit = 0) and in use (bit = 1) IDs.
> - * Initialised so that the reserved IDs are permanently marked as
> - * in use.
> - * @pend_rel_ids: CPU IDs that have been released by the trace source but not
> - * yet marked as available, to allow re-allocation to the same
> - * CPU during a perf session.
> - */
> -struct coresight_trace_id_map {
> - DECLARE_BITMAP(used_ids, CORESIGHT_TRACE_IDS_MAX);
> - DECLARE_BITMAP(pend_rel_ids, CORESIGHT_TRACE_IDS_MAX);
> -};
> -
> /* Allocate and release IDs for a single default trace ID map */
>
> /**
> diff --git a/include/linux/coresight.h b/include/linux/coresight.h
> index f09ace92176e..c16c61a8411d 100644
> --- a/include/linux/coresight.h
> +++ b/include/linux/coresight.h
> @@ -218,6 +218,24 @@ struct coresight_sysfs_link {
> const char *target_name;
> };
>
> +/* architecturally we have 128 IDs some of which are reserved */
> +#define CORESIGHT_TRACE_IDS_MAX 128
> +
> +/**
> + * Trace ID map.
> + *
> + * @used_ids: Bitmap to register available (bit = 0) and in use (bit = 1) IDs.
> + * Initialised so that the reserved IDs are permanently marked as
> + * in use.
> + * @pend_rel_ids: CPU IDs that have been released by the trace source but not
> + * yet marked as available, to allow re-allocation to the same
> + * CPU during a perf session.
> + */
> +struct coresight_trace_id_map {
> + DECLARE_BITMAP(used_ids, CORESIGHT_TRACE_IDS_MAX);
> + DECLARE_BITMAP(pend_rel_ids, CORESIGHT_TRACE_IDS_MAX);
> +};
> +
> /**
> * struct coresight_device - representation of a device as used by the framework
> * @pdata: Platform data with device connections associated to this device.
> --
> 2.34.1
>
Reviewed-by: Mike Leach <mike.leach@linaro.org>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
next prev parent reply other threads:[~2024-05-01 11:11 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-29 15:21 [PATCH 00/17] coresight: Use per-sink trace ID maps for Perf sessions James Clark
2024-04-29 15:21 ` [PATCH 01/17] perf cs-etm: Print error for new PERF_RECORD_AUX_OUTPUT_HW_ID versions James Clark
2024-05-07 3:47 ` Anshuman Khandual
2024-05-07 10:06 ` James Clark
2024-05-07 10:57 ` Anshuman Khandual
2024-05-07 14:54 ` Arnaldo Carvalho de Melo
2024-04-29 15:21 ` [PATCH 02/17] perf auxtrace: Allow number of queues to be specified James Clark
2024-04-30 6:36 ` Adrian Hunter
2024-05-07 4:26 ` Anshuman Khandual
2024-04-29 15:21 ` [PATCH 03/17] perf: cs-etm: Create decoders after both AUX and HW_ID search passes James Clark
2024-04-29 15:21 ` [PATCH 04/17] perf: cs-etm: Allocate queues for all CPUs James Clark
2024-04-29 15:21 ` [PATCH 05/17] perf: cs-etm: Move traceid_list to each queue James Clark
2024-04-29 15:21 ` [PATCH 06/17] perf: cs-etm: Create decoders based on the trace ID mappings James Clark
2024-04-29 15:21 ` [PATCH 07/17] perf: cs-etm: Support version 0.1 of HW_ID packets James Clark
2024-04-29 15:21 ` [PATCH 08/17] coresight: Remove unused stubs James Clark
2024-05-01 11:06 ` Mike Leach
2024-05-07 4:15 ` Anshuman Khandual
2024-04-29 15:21 ` [PATCH 09/17] coresight: Clarify comments around the PID of the sink owner James Clark
2024-05-01 11:07 ` Mike Leach
2024-05-07 4:25 ` Anshuman Khandual
2024-04-29 15:21 ` [PATCH 10/17] coresight: Move struct coresight_trace_id_map to common header James Clark
2024-05-01 11:11 ` Mike Leach [this message]
2024-05-07 5:50 ` Anshuman Khandual
2024-04-29 15:21 ` [PATCH 11/17] coresight: Expose map argument in trace ID API James Clark
2024-05-01 10:31 ` Mike Leach
2024-05-17 10:09 ` James Clark
2024-05-07 6:00 ` Anshuman Khandual
2024-04-29 15:21 ` [PATCH 11/17] coresight: Expose map arugment " James Clark
2024-04-29 15:30 ` James Clark
2024-04-29 15:21 ` [PATCH 12/17] coresight: Make CPU id map a property of a trace ID map James Clark
2024-05-07 6:22 ` Anshuman Khandual
2024-05-07 9:57 ` James Clark
2024-04-29 15:21 ` [PATCH 13/17] coresight: Pass trace ID map into source enable James Clark
2024-05-07 6:46 ` Anshuman Khandual
2024-05-07 10:49 ` Suzuki K Poulose
2024-04-29 15:22 ` [PATCH 14/17] coresight: Use per-sink trace ID maps for Perf sessions James Clark
2024-05-03 9:43 ` Mike Leach
2024-05-03 14:31 ` James Clark
2024-05-07 10:52 ` Suzuki K Poulose
2024-05-17 10:07 ` James Clark
2024-04-29 15:22 ` [PATCH 15/17] coresight: Remove pending trace ID release mechanism James Clark
2024-04-29 15:22 ` [PATCH 16/17] coresight: Re-emit trace IDs when the sink changes in per-thread mode James Clark
2024-05-07 11:05 ` Suzuki K Poulose
2024-05-17 10:01 ` James Clark
2024-04-29 15:22 ` [PATCH 17/17] coresight: Emit HW_IDs for all ETMs that are using the sink James Clark
2024-05-03 12:40 ` [PATCH 00/17] coresight: Use per-sink trace ID maps for Perf sessions Mike Leach
2024-05-17 10:45 ` James Clark
2024-05-03 20:23 ` Arnaldo Carvalho de Melo
2024-05-07 10:01 ` James Clark
2024-05-07 14:59 ` Arnaldo Carvalho de Melo
2024-05-07 11:02 ` Ganapatrao Kulkarni
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