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AJvYcCXCQnMCjpJBHUkOWPSjbQqJk8G2SOqO2Sq3/a1EOkWowoUNnLqZ1kkA8suZ87MTksocQHZ3ofr/ORJz7ireM9/S@vger.kernel.org X-Gm-Message-State: AOJu0YxFzPKJTMwBMn5IhB142tACemktE5f740eDcoh0Wx8LUQB5Zkff Mom0FA6Msib3SjuiopNgJCkrKDPCeEkg7lRuFANIomF69gBkz4sLLvBDt06HAzjaXC5fYQXw8wy FPmxnKpWf3yYJ30UHqF9cnO7cX/VuQspHTWrRq/6ZNg== X-Gm-Gg: ASbGncv34wO5+BhbjNuQ5L9d09xmF7X2br/n4uqiVuBsunkNj6s6ywsFjuF3bNRoWrk K+8YMH9egBQB8cgJMGndMTmN/ggkUfrLlABkL9c5sHrmWU0s6n4FBmw2gFfeVpepX+aAKsGWJRo 3qap/CLSKSChPdhJSxRMuVoCfZ+gU8L3n97EzjVbdrgZYkaNorvQbIYDDNIeTCLAAkGOi8I1ZGe KQsZQyLfICSB+N3ty0= X-Google-Smtp-Source: AGHT+IGmUn3ZM7jBX7D1YyhKjvaPN2e4dHa6K9n92Zz8n8QotO81v1sGyRseqSkkKtsFNnDYwv8ehf88vLMTTISTp9c= X-Received: by 2002:a05:6512:2316:b0:553:3a0a:1892 with SMTP id 2adb3069b0e04-55cc008637dmr3351518e87.15.1754905298946; Mon, 11 Aug 2025 02:41:38 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250805193955.798277-1-jesse@rivosinc.com> <20250805193955.798277-6-jesse@rivosinc.com> In-Reply-To: <20250805193955.798277-6-jesse@rivosinc.com> From: Anup Patel Date: Mon, 11 Aug 2025 15:11:27 +0530 X-Gm-Features: Ac12FXzX2WBI8Efn8ZEvJJb1ujk-ZIhK3W3ZYl12yeFcZ1SpyaqkJna1l4oNLS8 Message-ID: Subject: Re: [PATCH 5/8] riscv: hw_breakpoint: Use icount for single stepping To: Jesse Taube Cc: linux-riscv@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Oleg Nesterov , Kees Cook , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , Shuah Khan , Himanshu Chauhan , Charlie Jenkins , Samuel Holland , Conor Dooley , Deepak Gupta , Andrew Jones , Atish Patra , Mayuresh Chitale , Evan Green , WangYuli , Huacai Chen , Arnd Bergmann , Andrew Morton , Luis Chamberlain , "Mike Rapoport (Microsoft)" , Nam Cao , Yunhui Cui , Joel Granados , =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= , Sebastian Andrzej Siewior , Celeste Liu , Chunyan Zhang , Nylon Chen , Thomas Gleixner , =?UTF-8?Q?Thomas_Wei=C3=9Fschuh?= , Vincenzo Frascino , Joey Gouly , Akihiko Odaki , Ravi Bangoria , linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Jesse, On Wed, Aug 6, 2025 at 1:10=E2=80=AFAM Jesse Taube wro= te: > > The Sdtrig RISC-V ISA extension does not have a resume flag for > returning to and executing the instruction at the breakpoint. > To avoid skipping the instruction or looping, it is necessary to remove > the hardware breakpoint and single step. Use the icount feature of > Sdtrig to accomplish this. Use icount as default with an option to allow > software-based single stepping when hardware or SBI does not have > icount functionality, as it may cause unwanted side effects when reading > the instruction from memory. > > Signed-off-by: Jesse Taube > --- > OpenSBI implementation of sbi_debug_read_triggers does not return the > updated CSR values. There needs to be a check for working > sbi_debug_read_triggers before this works. > > https://lists.riscv.org/g/tech-prs/message/1476 > > RFC -> V1: > - Add dbtr_mode to rv_init_icount_trigger > - Add icount_triggered to check which breakpoint was triggered > - Fix typo: s/affects/effects > - Move HW_BREAKPOINT_COMPUTE_STEP to Platform type > --- > arch/riscv/Kconfig | 11 ++ > arch/riscv/kernel/hw_breakpoint.c | 179 +++++++++++++++++++++++++++--- > 2 files changed, 172 insertions(+), 18 deletions(-) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index fd8b62cdc6f5..37f01ed199f3 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -546,6 +546,17 @@ config RISCV_COMBO_SPINLOCKS > > endchoice > > +config HW_BREAKPOINT_COMPUTE_STEP > + bool "Allow computing hardware breakpoint step address" > + default n > + depends on HAVE_HW_BREAKPOINT > + help > + Select this option if hardware breakpoints are desired, but > + hardware or SBI does not have icount functionality. This may ca= use > + unwanted side effects when reading the instruction from memory. > + > + If unsure, say N. > + We expect the same kernel image to work on a platform with icount triggers and without icount triggers. Please drop this kconfig option. The decision of falling back to computing hardware breakpoint step address should be at boot-time and not compile-time. Regards, Anup