From: Namhyung Kim <namhyung@kernel.org>
To: Ravi Bangoria <ravi.bangoria@amd.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>,
Kan Liang <kan.liang@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Ian Rogers <irogers@google.com>,
Peter Zijlstra <peterz@infradead.org>,
rrichter@amd.com, Ingo Molnar <mingo@redhat.com>,
Mark Rutland <mark.rutland@arm.com>,
Thomas Gleixner <tglx@linutronix.de>,
Borislav Petkov <bp@alien8.de>, James Clark <james.clark@arm.com>,
Leo Yan <leo.yan@linaro.org>, Andi Kleen <ak@linux.intel.com>,
Stephane Eranian <eranian@google.com>,
like.xu.linux@gmail.com, x86@kernel.org,
linux-perf-users <linux-perf-users@vger.kernel.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
Sandipan Das <sandipan.das@amd.com>,
ananth.narayan@amd.com, Kim Phillips <kim.phillips@amd.com>,
santosh.shukla@amd.com
Subject: Re: [PATCH v5 4/8] perf headers: Store pmu caps in an array of strings
Date: Thu, 2 Jun 2022 14:37:20 -0700 [thread overview]
Message-ID: <CAM9d7cgraWne_NRGFqscWbYSx5nue_A2fJCQ-OaQBTC3g0eijg@mail.gmail.com> (raw)
In-Reply-To: <20220601032608.1034-5-ravi.bangoria@amd.com>
On Tue, May 31, 2022 at 8:28 PM Ravi Bangoria <ravi.bangoria@amd.com> wrote:
>
> Currently all capabilities are stored in a single string separated
> by NULL character. Instead, store them in an array which makes
> searching of capability easier.
>
> Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
> ---
[SNIP]
> @@ -3231,12 +3226,16 @@ static int process_per_cpu_pmu_caps(struct feat_fd *ff, int *nr_cpu_pmu_caps,
> if (!value)
> goto free_name;
>
> - if (strbuf_addf(&sb, "%s=%s", name, value) < 0)
> + name_size = strlen(name);
> + value_size = strlen(value);
> + ptr = zalloc(sizeof(char) * (name_size + value_size + 2));
> + if (!ptr)
> goto free_value;
>
> - /* include a NULL character at the end */
> - if (strbuf_add(&sb, "", 1) < 0)
> - goto free_value;
> + memcpy(ptr, name, name_size);
> + ptr[name_size] = '=';
> + memcpy(ptr + name_size + 1, value, value_size);
What about using asprintf() instead?
Thanks,
Namhyung
> + (*cpu_pmu_caps)[i] = ptr;
>
> if (!strcmp(name, "branches"))
> *max_branches = atoi(value);
> @@ -3244,7 +3243,7 @@ static int process_per_cpu_pmu_caps(struct feat_fd *ff, int *nr_cpu_pmu_caps,
> free(value);
> free(name);
> }
> - *cpu_pmu_caps = strbuf_detach(&sb, NULL);
> + *nr_cpu_pmu_caps = nr_caps;
> return 0;
>
> free_value:
> @@ -3252,16 +3251,24 @@ static int process_per_cpu_pmu_caps(struct feat_fd *ff, int *nr_cpu_pmu_caps,
> free_name:
> free(name);
> error:
> - strbuf_release(&sb);
> + for (; i > 0; i--)
> + free((*cpu_pmu_caps)[i - 1]);
> + free(*cpu_pmu_caps);
> + *cpu_pmu_caps = NULL;
> + *nr_cpu_pmu_caps = 0;
> return -1;
> }
>
> static int process_cpu_pmu_caps(struct feat_fd *ff,
> void *data __maybe_unused)
> {
> - return process_per_cpu_pmu_caps(ff, &ff->ph->env.nr_cpu_pmu_caps,
> + int ret = process_per_cpu_pmu_caps(ff, &ff->ph->env.nr_cpu_pmu_caps,
> &ff->ph->env.cpu_pmu_caps,
> &ff->ph->env.max_branches);
> +
> + if (!ret && !ff->ph->env.cpu_pmu_caps)
> + pr_debug("cpu pmu capabilities not available\n");
> + return ret;
> }
>
> static int process_hybrid_cpu_pmu_caps(struct feat_fd *ff,
> @@ -3270,6 +3277,7 @@ static int process_hybrid_cpu_pmu_caps(struct feat_fd *ff,
> struct hybrid_cpc_node *nodes;
> u32 nr_pmu, i;
> int ret;
> + int j;
>
> if (do_read_u32(ff, &nr_pmu))
> return -1;
> @@ -3297,6 +3305,8 @@ static int process_hybrid_cpu_pmu_caps(struct feat_fd *ff,
> ret = -1;
> goto err;
> }
> + if (!n->nr_cpu_pmu_caps)
> + pr_debug("%s pmu capabilities not available\n", n->pmu_name);
> }
>
> ff->ph->env.nr_hybrid_cpc_nodes = nr_pmu;
> @@ -3305,6 +3315,8 @@ static int process_hybrid_cpu_pmu_caps(struct feat_fd *ff,
>
> err:
> for (i = 0; i < nr_pmu; i++) {
> + for (j = 0; j < nodes[i].nr_cpu_pmu_caps; j++)
> + free(nodes[i].cpu_pmu_caps[j]);
> free(nodes[i].cpu_pmu_caps);
> free(nodes[i].pmu_name);
> }
> --
> 2.31.1
>
next prev parent reply other threads:[~2022-06-02 21:37 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-01 3:26 [PATCH v5 0/8] perf/amd: Zen4 IBS extensions support (tool changes) Ravi Bangoria
2022-06-01 3:26 ` [PATCH v5 1/8] perf record ibs: Warn about sampling period skew Ravi Bangoria
2022-06-02 20:30 ` Namhyung Kim
2022-06-03 5:12 ` Ravi Bangoria
2022-06-03 5:28 ` Ravi Bangoria
2022-06-03 19:25 ` Arnaldo Carvalho de Melo
2022-06-01 3:26 ` [PATCH v5 2/8] perf tool: Parse pmu caps sysfs only once Ravi Bangoria
2022-06-01 13:35 ` Liang, Kan
2022-06-01 13:51 ` Ravi Bangoria
2022-06-01 13:55 ` Liang, Kan
2022-06-01 3:26 ` [PATCH v5 3/8] perf headers: Pass "cpu" pmu name while printing caps Ravi Bangoria
2022-06-01 13:35 ` Liang, Kan
2022-06-01 3:26 ` [PATCH v5 4/8] perf headers: Store pmu caps in an array of strings Ravi Bangoria
2022-06-01 13:36 ` Liang, Kan
2022-06-02 21:37 ` Namhyung Kim [this message]
2022-06-03 5:20 ` Ravi Bangoria
2022-06-01 3:26 ` [PATCH v5 5/8] perf headers: Record non-cpu pmu capabilities Ravi Bangoria
2022-06-01 13:37 ` Liang, Kan
2022-06-01 13:58 ` Liang, Kan
2022-06-01 3:26 ` [PATCH v5 6/8] perf/x86/ibs: Add new IBS register bits into header Ravi Bangoria
2022-06-02 21:48 ` Namhyung Kim
2022-06-03 5:24 ` Ravi Bangoria
2022-06-01 3:26 ` [PATCH v5 7/8] perf tool ibs: Sync amd ibs header file Ravi Bangoria
2022-06-01 3:26 ` [PATCH v5 8/8] perf script ibs: Support new IBS bits in raw trace dump Ravi Bangoria
2022-06-01 14:04 ` [PATCH v5 0/8] perf/amd: Zen4 IBS extensions support (tool changes) Liang, Kan
2022-06-01 14:10 ` Ravi Bangoria
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