From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C4F5EB64D8 for ; Fri, 16 Jun 2023 08:43:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343594AbjFPInf (ORCPT ); Fri, 16 Jun 2023 04:43:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343607AbjFPInc (ORCPT ); Fri, 16 Jun 2023 04:43:32 -0400 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C23E5199 for ; Fri, 16 Jun 2023 01:43:29 -0700 (PDT) Received: by mail-lj1-x22f.google.com with SMTP id 38308e7fff4ca-2b34eb53208so6853291fa.0 for ; Fri, 16 Jun 2023 01:43:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=atishpatra.org; s=google; t=1686905008; x=1689497008; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=jDKNwc2spJwBfD2I0zIbFW0EXN11ktfXXRri1gY5Wq4=; b=Q4BVOMxjOIj+1lvfbkrCmoferkJ4DrgoK2bY1m2+REfJQMIq1E8wARoLRu1Ucq0fch KW8AVDqi6q48jF0cCigWx4G9koByTKk0TO8dXqh6RQKVeUiQ5XlKID3vJ5479apMgKNj px0XvIXdo0H2dmHBJRA9CIMQt3MgDbcNsylek= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686905008; x=1689497008; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jDKNwc2spJwBfD2I0zIbFW0EXN11ktfXXRri1gY5Wq4=; b=VxMtqGZC+r+gcRDUIGzIjcbJiG7sOq/2JWktEqhL5CSEKb//FOe9szJAYeDJzkQwI/ UZ5v65ri5AU81mDRJtBKC9fKaTeQPLcqncbbv895z+x8GYFMkfE0RhruRMctm8xU1dCM 4usptoD4SxlGgxDUktjXdb9p2FYdQSbOdAGFvoo3ne7CddumI1sbO1jH0dupLwPMf2BI O+XSAXiYTRQHBN86MQeF+oN21HBrQOuED9m4NKlXUtgXTbenXaiuWMwd3i+Qls3uucBc LfYlU+NTdw+un691YlI+KGV4jR5MrVnVqMHi/6tQBKQyBWZQXqsfb77atqqcORQoc3WC XqpA== X-Gm-Message-State: AC+VfDw4ytW6dmBiALDS52SUHgj8zj+s41TCsSFp7ZkErBB4WNBzYyjX 9dECM4IMM5qnwFShpZYmBT5xcPbdhwNdOn1ATeRL X-Google-Smtp-Source: ACHHUZ588No8rZTW5BgVANgGiSevYvr7PcGyiQIzkpCtRm5EWtTsAu2/r8c06MBm/GyhWVIvHZI+/K/g+jEjYCbGYpk= X-Received: by 2002:a05:651c:150:b0:2b0:919e:4265 with SMTP id c16-20020a05651c015000b002b0919e4265mr362266ljd.21.1686905008073; Fri, 16 Jun 2023 01:43:28 -0700 (PDT) MIME-Version: 1.0 References: <20230512085321.13259-1-alexghiti@rivosinc.com> <20230512085321.13259-10-alexghiti@rivosinc.com> In-Reply-To: <20230512085321.13259-10-alexghiti@rivosinc.com> From: Atish Patra Date: Fri, 16 Jun 2023 01:43:16 -0700 Message-ID: Subject: Re: [PATCH v2 09/10] tools: lib: perf: Implement riscv mmap support To: Alexandre Ghiti Cc: Jonathan Corbet , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Will Deacon , Rob Herring , Andrew Jones , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-perf-users@vger.kernel.org On Fri, May 12, 2023 at 2:03=E2=80=AFAM Alexandre Ghiti wrote: > > riscv now support mmaping hardware counters so add what's needed to > take advantage of that in libperf. > > Signed-off-by: Alexandre Ghiti > --- > tools/lib/perf/mmap.c | 65 +++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 65 insertions(+) > > diff --git a/tools/lib/perf/mmap.c b/tools/lib/perf/mmap.c > index 0d1634cedf44..65f250e0ef92 100644 > --- a/tools/lib/perf/mmap.c > +++ b/tools/lib/perf/mmap.c > @@ -392,6 +392,71 @@ static u64 read_perf_counter(unsigned int counter) > > static u64 read_timestamp(void) { return read_sysreg(cntvct_el0); } > > +#elif __riscv_xlen =3D=3D 64 > + This is applicable for RV32 as well. No ? otherwise, you won't need CSR_CYCLEH > +#define CSR_CYCLE 0xc00 > +#define CSR_TIME 0xc01 > +#define CSR_CYCLEH 0xc80 > + > +#define csr_read(csr) \ > +({ \ > + register unsigned long __v; \ > + __asm__ __volatile__ ("csrr %0, " #csr \ > + : "=3Dr" (__v) : \ > + : "memory"); \ > + __v; \ > +}) > + > +static unsigned long csr_read_num(int csr_num) > +{ > +#define switchcase_csr_read(__csr_num, __val) {\ > + case __csr_num: \ > + __val =3D csr_read(__csr_num); \ > + break; } > +#define switchcase_csr_read_2(__csr_num, __val) {\ > + switchcase_csr_read(__csr_num + 0, __val) \ > + switchcase_csr_read(__csr_num + 1, __val)} > +#define switchcase_csr_read_4(__csr_num, __val) {\ > + switchcase_csr_read_2(__csr_num + 0, __val) \ > + switchcase_csr_read_2(__csr_num + 2, __val)} > +#define switchcase_csr_read_8(__csr_num, __val) {\ > + switchcase_csr_read_4(__csr_num + 0, __val) \ > + switchcase_csr_read_4(__csr_num + 4, __val)} > +#define switchcase_csr_read_16(__csr_num, __val) {\ > + switchcase_csr_read_8(__csr_num + 0, __val) \ > + switchcase_csr_read_8(__csr_num + 8, __val)} > +#define switchcase_csr_read_32(__csr_num, __val) {\ > + switchcase_csr_read_16(__csr_num + 0, __val) \ > + switchcase_csr_read_16(__csr_num + 16, __val)} > + > + unsigned long ret =3D 0; > + > + switch (csr_num) { > + switchcase_csr_read_32(CSR_CYCLE, ret) > + switchcase_csr_read_32(CSR_CYCLEH, ret) > + default: > + break; > + } > + > + return ret; > +#undef switchcase_csr_read_32 > +#undef switchcase_csr_read_16 > +#undef switchcase_csr_read_8 > +#undef switchcase_csr_read_4 > +#undef switchcase_csr_read_2 > +#undef switchcase_csr_read > +} > + > +static u64 read_perf_counter(unsigned int counter) > +{ > + return csr_read_num(CSR_CYCLE + counter); > +} > + > +static u64 read_timestamp(void) > +{ > + return csr_read_num(CSR_TIME); > +} > + > #else > static u64 read_perf_counter(unsigned int counter __maybe_unused) { retu= rn 0; } > static u64 read_timestamp(void) { return 0; } > -- > 2.37.2 > --=20 Regards, Atish