From: Atish Patra <atishp@atishpatra.org>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: Alexandre Ghiti <alexghiti@rivosinc.com>,
Jonathan Corbet <corbet@lwn.net>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Anup Patel <anup@brainfault.org>, Will Deacon <will@kernel.org>,
Rob Herring <robh@kernel.org>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-perf-users@vger.kernel.org,
linux-riscv@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 08/10] Documentation: admin-guide: Add riscv sysctl_perf_user_access
Date: Wed, 31 May 2023 10:08:56 -0700 [thread overview]
Message-ID: <CAOnJCU+sda3UaOvC3Si4TT3nvibUSEOwmx94eQK-9ouvG4=ovQ@mail.gmail.com> (raw)
In-Reply-To: <20230531-0707dc46df8078cd92711314@orel>
On Wed, May 31, 2023 at 8:07 AM Andrew Jones <ajones@ventanamicro.com> wrote:
>
> On Fri, May 12, 2023 at 10:53:19AM +0200, Alexandre Ghiti wrote:
> > riscv now uses this sysctl so document its usage for this architecture.
> >
> > Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> > ---
> > Documentation/admin-guide/sysctl/kernel.rst | 24 +++++++++++++++++----
> > 1 file changed, 20 insertions(+), 4 deletions(-)
> >
> > diff --git a/Documentation/admin-guide/sysctl/kernel.rst b/Documentation/admin-guide/sysctl/kernel.rst
> > index 4b7bfea28cd7..93cd518ca94b 100644
> > --- a/Documentation/admin-guide/sysctl/kernel.rst
> > +++ b/Documentation/admin-guide/sysctl/kernel.rst
> > @@ -941,16 +941,32 @@ enabled, otherwise writing to this file will return ``-EBUSY``.
> > The default value is 8.
> >
> >
> > -perf_user_access (arm64 only)
> > -=================================
> > +perf_user_access (arm64 and riscv only)
> > +=======================================
> > +
> > +Controls user space access for reading perf event counters.
> >
> > -Controls user space access for reading perf event counters. When set to 1,
> > -user space can read performance monitor counter registers directly.
> > +arm64
> > +=====
> >
> > The default value is 0 (access disabled).
> > +When set to 1, user space can read performance monitor counter registers
> > +directly.
> >
> > See Documentation/arm64/perf.rst for more information.
> >
> > +riscv
> > +=====
> > +
> > +When set to 0, user access is disabled.
> > +
> > +When set to 1, user space can read performance monitor counter registers
> > +directly only through perf, any direct access without perf intervention will
> > +trigger an illegal instruction.
> > +
> > +The default value is 2, which enables legacy mode (user space has direct
> > +access to cycle, time and insret CSRs only). Note that this legacy value
> > +is deprecated and will be removed once all userspace applications are fixed.
>
> All modes can access the time CSR so I'm not sure if it should be pointed
> out here as if it's an exception. Maybe we shouldn't point it out at all
> or we should point it out for all three?
>
Valid point. Thanks Drew.
In the future, we probably want to support prctl
(PR_SET_TSC/SECCOMP_MODE_STRICT) to disable even
time CSR access. I don't think there is any use case for it right now.
> Thanks,
> drew
--
Regards,
Atish
next prev parent reply other threads:[~2023-05-31 17:09 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-12 8:53 [PATCH v2 00/10] riscv: Allow userspace to directly access perf counters Alexandre Ghiti
2023-05-12 8:53 ` [PATCH v2 01/10] perf: Fix wrong comment about default event_idx Alexandre Ghiti
2023-05-31 13:54 ` Andrew Jones
2023-06-15 7:10 ` Alexandre Ghiti
2023-06-15 8:24 ` Atish Patra
2023-05-12 8:53 ` [PATCH v2 02/10] include: riscv: Fix wrong include guard in riscv_pmu.h Alexandre Ghiti
2023-05-31 13:56 ` Andrew Jones
2023-06-15 8:36 ` Atish Patra
2023-05-12 8:53 ` [PATCH v2 03/10] riscv: Make legacy counter enum match the HW numbering Alexandre Ghiti
2023-05-31 14:01 ` Andrew Jones
2023-06-15 7:16 ` Alexandre Ghiti
2023-05-12 8:53 ` [PATCH v2 04/10] drivers: perf: Rename riscv pmu driver Alexandre Ghiti
2023-05-31 14:09 ` Andrew Jones
2023-06-15 7:25 ` Alexandre Ghiti
2023-06-15 8:34 ` Atish Patra
2023-05-12 8:53 ` [PATCH v2 05/10] riscv: Prepare for user-space perf event mmap support Alexandre Ghiti
2023-05-31 14:24 ` Andrew Jones
2023-06-16 8:28 ` Atish Patra
2023-06-16 8:56 ` Alexandre Ghiti
2023-06-20 15:27 ` Atish Patra
2023-05-12 8:53 ` [PATCH v2 06/10] drivers: perf: Implement perf event mmap support in the legacy backend Alexandre Ghiti
2023-05-31 14:27 ` Andrew Jones
2023-06-15 7:38 ` Alexandre Ghiti
2023-05-12 8:53 ` [PATCH v2 07/10] drivers: perf: Implement perf event mmap support in the SBI backend Alexandre Ghiti
2023-05-31 15:02 ` Andrew Jones
2023-06-15 8:41 ` Atish Patra
2023-06-15 13:27 ` Heinrich Schuchardt
2023-06-16 7:44 ` Atish Patra
2023-06-15 9:52 ` Alexandre Ghiti
2023-05-12 8:53 ` [PATCH v2 08/10] Documentation: admin-guide: Add riscv sysctl_perf_user_access Alexandre Ghiti
2023-05-31 15:07 ` Andrew Jones
2023-05-31 17:08 ` Atish Patra [this message]
2023-06-15 10:00 ` Alexandre Ghiti
2023-05-12 8:53 ` [PATCH v2 09/10] tools: lib: perf: Implement riscv mmap support Alexandre Ghiti
2023-05-31 15:12 ` Andrew Jones
2023-06-16 8:43 ` Atish Patra
2023-06-16 9:06 ` Alexandre Ghiti
2023-06-19 19:04 ` Atish Patra
2023-05-12 8:53 ` [PATCH v2 10/10] perf: tests: Adapt mmap-basic.c for riscv Alexandre Ghiti
2023-05-31 15:15 ` Andrew Jones
2023-06-05 13:53 ` Arnaldo Carvalho de Melo
2023-06-05 14:02 ` Alexandre Ghiti
[not found] ` <CAHVXubhofC+WaSysWaxcTA2GdJAF8kTD3COBeQDAy25af_rSLg@mail.gmail.com>
2023-06-05 14:31 ` Arnaldo Carvalho de Melo
2023-06-15 10:02 ` Alexandre Ghiti
2023-05-15 17:50 ` [PATCH v2 00/10] riscv: Allow userspace to directly access perf counters Conor Dooley
2023-06-21 23:37 ` Palmer Dabbelt
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