From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93937C6FD18 for ; Tue, 18 Apr 2023 20:30:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230408AbjDRUad (ORCPT ); Tue, 18 Apr 2023 16:30:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230153AbjDRUac (ORCPT ); Tue, 18 Apr 2023 16:30:32 -0400 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 541BB1BE for ; Tue, 18 Apr 2023 13:30:31 -0700 (PDT) Received: by mail-pj1-x1030.google.com with SMTP id 98e67ed59e1d1-2470e93ea71so1730695a91.0 for ; Tue, 18 Apr 2023 13:30:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=atishpatra.org; s=google; t=1681849831; x=1684441831; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=758KJFnubLFSsZj7NLSbl2wQ+MQOeQGEXb82zXsrHA8=; b=JKWc07Hsa1AIwKVKIMzXI4sw331w8kX1TDKqtQB//KSPOSUQN+tk39Ofo87lgk87cs A++4AkL4VO7Zo172B6EmKiVr7FrbMePdElPSloCsouI2E/r/+XOY/fDC60aCptlCrI9z Pj+V02e4O7mTkISl5wP8rj3Y1EWU2fzkx9GVY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681849831; x=1684441831; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=758KJFnubLFSsZj7NLSbl2wQ+MQOeQGEXb82zXsrHA8=; b=LCA19juk2DLPf1Dh9farkyUNBMQIt+cYdmH1F6J3Y/nqKunkw4m0F8oOSw1pEGcOAw mcy+1D9rXuiX+9fi+ALZZ0xHJU9JzNvi9uo7+rSnGJKNGhTX3JIx74ZEN4M5uGOgdIQ0 xZxDaVgG9sD96i8vCd3/yU+0FpnSxV93wDTPad5cmLXN/uCfN3dT+DMKfEc/XRFg65LE C7mCb0RWIpJIJvnUExuixkGb7Pf45LnwCmp1ptkArkPOpbBQSk3yHIUHOTD3cUvB0Um8 eg4jXoCQQWiYO6Cr8fDQIO0kJoj3KwgiY/qoZ4LMpR3JUtk9NYGbNyv6vdmROb6fARaE HSow== X-Gm-Message-State: AAQBX9dD2pV6upYFRcK0o6Pn/fLoBp0oXcvLW7AUxEo89m+gxi8bAp4i 081avf6i38ogbOehn0t30cz9qt4tUgkQyKG+k+5c X-Google-Smtp-Source: AKy350ZIg+M7FnY7uohsy0MLIS1rdUP3e5Y8mF0C/rJh0Ab5JDC3yj3RoFOx5gy5nC7akfL3LOBt0QioDaAyr1DFD3g= X-Received: by 2002:a17:90a:4706:b0:23d:1121:f211 with SMTP id h6-20020a17090a470600b0023d1121f211mr293761pjg.5.1681849830738; Tue, 18 Apr 2023 13:30:30 -0700 (PDT) MIME-Version: 1.0 References: <20230413161725.195417-1-alexghiti@rivosinc.com> In-Reply-To: From: Atish Patra Date: Wed, 19 Apr 2023 02:00:18 +0530 Message-ID: Subject: Re: [PATCH 0/4] riscv: Allow userspace to directly access perf counters To: Ian Rogers Cc: David Laight , Alexandre Ghiti , Jonathan Corbet , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Will Deacon , Rob Herring , "linux-doc@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-perf-users@vger.kernel.org" , "linux-riscv@lists.infradead.org" , "linux-arm-kernel@lists.infradead.org" , paranlee Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-perf-users@vger.kernel.org On Tue, Apr 18, 2023 at 11:46=E2=80=AFPM Ian Rogers wr= ote: > > On Tue, Apr 18, 2023 at 9:43=E2=80=AFAM Atish Patra wrote: > > > > On Fri, Apr 14, 2023 at 2:40=E2=80=AFAM David Laight wrote: > > > > > > From: Atish Patra > > > > Sent: 13 April 2023 20:18 > > > > > > > > On Thu, Apr 13, 2023 at 9:47=E2=80=AFPM Alexandre Ghiti wrote: > > > > > > > > > > riscv used to allow direct access to cycle/time/instret counters, > > > > > bypassing the perf framework, this patchset intends to allow the = user to > > > > > mmap any counter when accessed through perf. But we can't break t= he > > > > > existing behaviour so we introduce a sysctl perf_user_access like= arm64 > > > > > does, which defaults to the legacy mode described above. > > > > > > > > > > > > > It would be good provide additional direction for user space packag= es: > > > > > > > > The legacy behavior is supported for now in order to avoid breaking > > > > existing software. > > > > However, reading counters directly without perf interaction may > > > > provide incorrect values which > > > > the userspace software must avoid. We are hoping that the user spac= e > > > > packages which > > > > read the cycle/instret directly, will move to the proper interface > > > > eventually if they actually need it. > > > > Most of the users are supposed to read "time" instead of "cycle" if > > > > they intend to read timestamps. > > > > > > If you are trying to measure the performance of short code > > > fragments then you need pretty much raw access directly to > > > the cycle/clock count register. > > > > > > I've done this on x86 to compare the actual cycle times > > > of different implementations of the IP checksum loop > > > (and compare them to the theoretical limit). > > > The perf framework just added far too much latency, > > > only directly reading the cpu registers gave anything > > > like reliable (and consistent) answers. > > > > > > > This series allows direct access to the counters once configured > > through the perf. > > Earlier the cycle/instret counters are directly exposed to the > > userspace without kernel/perf frameworking knowing > > when/which user space application is reading it. That has security impl= ications. > > > > With this series applied, the user space application just needs to > > configure the event (cycle/instret) through perf syscall. > > Once configured, the userspace application can find out the counter > > information from the mmap & directly > > read the counter. There is no latency while reading the counters. > > > > This mechanism allows stop/clear the counters when the requesting task > > is not running. It also takes care of context switching > > which may result in invalid values as you mentioned below. This is > > nothing new and all other arch (x86, ARM64) allow user space > > counter read through the same mechanism. > > > > Here is the relevant upstream discussion: > > https://lore.kernel.org/lkml/Y7wLa7I2hlz3rKw%2F@hirez.programming.kicks= -ass.net/T/ > > > > ARM64: > > https://docs.kernel.org/arm64/perf.html?highlight=3Dperf_user_access#pe= rf-userspace-pmu-hardware-counter-access > > > > example usage in x86: > > https://github.com/andikleen/pmu-tools/blob/master/jevents/rdpmc.c > > The canonical implementation of this should be: > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/t= ools/lib/perf/mmap.c#n400 Thanks for sharing the libperf implementation. > which is updated in these patches but the tests are not: > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/t= ools/perf/tests/mmap-basic.c#n287 > Which appears to be an oversight. The tests display some differences Yes. It's an oversight. We should make sure that perf mmap tests pass for RISC-V as well. > between x86 and aarch64 that have assumed userspace hardware counter > access, and everything else that it is assumed don't. > > Thanks, > Ian > > > > Clearly process switches (especially cpu migrations) cause > > > problems, but they are obviously invalid values and can > > > be ignored. > > > > > > So while a lot of uses may be 'happy' with the values the > > > perf framework gives, sometimes you do need to directly > > > read the relevant registers. > > > > > > David > > > > > > - > > > Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes,= MK1 1PT, UK > > > Registration No: 1397386 (Wales) > > > > > > > > -- > > Regards, > > Atish -- Regards, Atish