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charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Nov 13, 2025 at 12:29=E2=80=AFAM Thomas Richter wrote: > > On s390 z/VM systems (linux guest on s390 LPAR) this happens: > > # perf test 96 97 > 96: perf all metricgroups test : FAILED! > 97: perf all metrics test : FAILED! > > This test works on the linux repo: > # perf test 95 96 > 95: perf all metricgroups test : Ok > 96: perf all metrics test : Ok > > On both systems the command > # ./perf list --raw-dump metric > cpi est_cpi finite_cpi l1mp l2p l3p l4lp l4rp memp prbstate scpl1m \ > tlb_miss tlb_percent transaction > shows the same list of available metrics. > > On z/VM the CPU Measurement facilities do not exist: > > # ll /sys/devices/cpum_cf/events > ls: cannot access '/sys/devices/cpum_cf/events': No such file or directo= ry > # > > The json files for s390 define the metric 'cpi' in > arch/s390/cf_z16/transaction.json: > > { > "BriefDescription": "Cycles per Instruction", > "MetricName": "cpi", > "MetricExpr": "CPU_CYCLES / INSTRUCTIONS \ > if has_event(INSTRUCTIONS) else 0" > }, > > The macro has_event(INSTRUCTIONS) now refers to a legacy event which > always exists. It is always true even when the hardware does not > support this event. Change the has_event(xxx) to check for a hardware > event not available, for example CPU_CYCLES. > > Fixes: 0012e0fa221b ("perf jevents: Add legacy-hardware and legacy-cache = json") > Suggested by: Ian Rogers > Signed-off-by: Thomas Richter This fix is equivalent to: https://lore.kernel.org/lkml/20251112162439.1553368-1-irogers@google.com/ I'm easy about which one is picked up, the commit message here has more det= ail. Reviewed-by: Ian Rogers Thanks, Ian > --- > tools/perf/pmu-events/arch/s390/cf_z16/transaction.json | 8 ++++---- > tools/perf/pmu-events/arch/s390/cf_z17/transaction.json | 8 ++++---- > 2 files changed, 8 insertions(+), 8 deletions(-) > > diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json b/to= ols/perf/pmu-events/arch/s390/cf_z16/transaction.json > index 3ab1d3a6638c..26c550621d6a 100644 > --- a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json > +++ b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json > @@ -7,17 +7,17 @@ > { > "BriefDescription": "Cycles per Instruction", > "MetricName": "cpi", > - "MetricExpr": "CPU_CYCLES / INSTRUCTIONS if has_event(INSTRUCTIONS) = else 0" > + "MetricExpr": "CPU_CYCLES / INSTRUCTIONS if has_event(CPU_CYCLES) el= se 0" > }, > { > "BriefDescription": "Problem State Instruction Ratio", > "MetricName": "prbstate", > - "MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100 if = has_event(INSTRUCTIONS) else 0" > + "MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100 if = has_event(CPU_CYCLES) else 0" > }, > { > "BriefDescription": "Level One Miss per 100 Instructions", > "MetricName": "l1mp", > - "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * = 100 if has_event(INSTRUCTIONS) else 0" > + "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * = 100 if has_event(CPU_CYCLES) else 0" > }, > { > "BriefDescription": "Percentage sourced from Level 2 cache", > @@ -52,7 +52,7 @@ > { > "BriefDescription": "Estimated Instruction Complexity CPI infinite L= evel 1", > "MetricName": "est_cpi", > - "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INST= RUCTIONS) if has_event(INSTRUCTIONS) else 0" > + "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INST= RUCTIONS) if has_event(CPU_CYCLES) else 0" > }, > { > "BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss", > diff --git a/tools/perf/pmu-events/arch/s390/cf_z17/transaction.json b/to= ols/perf/pmu-events/arch/s390/cf_z17/transaction.json > index 74df533c8b6f..4d296e0c8934 100644 > --- a/tools/perf/pmu-events/arch/s390/cf_z17/transaction.json > +++ b/tools/perf/pmu-events/arch/s390/cf_z17/transaction.json > @@ -7,17 +7,17 @@ > { > "BriefDescription": "Cycles per Instruction", > "MetricName": "cpi", > - "MetricExpr": "CPU_CYCLES / INSTRUCTIONS if has_event(INSTRUCTIONS) = else 0" > + "MetricExpr": "CPU_CYCLES / INSTRUCTIONS if has_event(CPU_CYCLES) el= se 0" > }, > { > "BriefDescription": "Problem State Instruction Ratio", > "MetricName": "prbstate", > - "MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100 if = has_event(INSTRUCTIONS) else 0" > + "MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100 if = has_event(CPU_CYCLES) else 0" > }, > { > "BriefDescription": "Level One Miss per 100 Instructions", > "MetricName": "l1mp", > - "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * = 100 if has_event(INSTRUCTIONS) else 0" > + "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * = 100 if has_event(CPU_CYCLES) else 0" > }, > { > "BriefDescription": "Percentage sourced from Level 2 cache", > @@ -52,7 +52,7 @@ > { > "BriefDescription": "Estimated Instruction Complexity CPI infinite L= evel 1", > "MetricName": "est_cpi", > - "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INST= RUCTIONS) if has_event(INSTRUCTIONS) else 0" > + "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INST= RUCTIONS) if has_event(CPU_CYCLES) else 0" > }, > { > "BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss", > -- > 2.51.1 >