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AJvYcCWu7eaW7aitQ+IU3RbLSCeazQivKbErGShBP/RQaCGiTgbli1tOzsdTWgsN7UEzvyILtoQauXeaa8a+/eDuw4q/6NcMpvvNHk632P8BWoZJ5Q== X-Gm-Message-State: AOJu0YxACFMjs2MoWXg64OGb8ZFBDAmbDLtRdj0rqtShv3MSEuXm2P2n 5wPV2vAOCpwDvEccNH9TkmAjW0FGGX2/W6t5dCSsJsuwwETSNksNNhy8RXOK6oNcWt+8uNiOiyp umygvjuOkjSMUWhuvcsEZqImF/N6IaA7h3T2K X-Google-Smtp-Source: AGHT+IEFfX0IrtvdULyN66f10heNy91Xt+GeYOFUXi4nvaPeuN2PAOzDNm7Vw0JcnmVVNOeGCTZgBZtFwdAB2xtB2ts= X-Received: by 2002:ac8:1286:0:b0:43a:2e2b:eec with SMTP id y6-20020ac81286000000b0043a2e2b0eecmr169202qti.2.1713971946704; Wed, 24 Apr 2024 08:19:06 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240416061533.921723-1-irogers@google.com> <20240416061533.921723-14-irogers@google.com> <7df3ff63-a421-42cc-bcaa-b0254ff6a0e8@linux.intel.com> In-Reply-To: <7df3ff63-a421-42cc-bcaa-b0254ff6a0e8@linux.intel.com> From: Ian Rogers Date: Wed, 24 Apr 2024 08:18:52 -0700 Message-ID: Subject: Re: [PATCH v2 13/16] perf parse-events: Improvements to modifier parsing To: "Liang, Kan" Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Adrian Hunter , James Clark , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, Atish Patra , linux-riscv@lists.infradead.org, Beeman Strong Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, Apr 19, 2024 at 6:20=E2=80=AFAM Liang, Kan wrote: > > > > On 2024-04-19 2:22 a.m., Ian Rogers wrote: > >>> + /* Simple modifiers copied to the evsel. */ > >>> + if (mod.precise) { > >>> + u8 precise =3D evsel->core.attr.precise_ip + mo= d.precise; > >>> + /* > >>> + * precise ip: > >>> + * > >>> + * 0 - SAMPLE_IP can have arbitrary skid > >>> + * 1 - SAMPLE_IP must have constant skid > >>> + * 2 - SAMPLE_IP requested to have 0 skid > >>> + * 3 - SAMPLE_IP must have 0 skid > >>> + * > >>> + * See also PERF_RECORD_MISC_EXACT_IP > >>> + */ > >>> + if (precise > 3) { > >> The pmu_max_precise() should return the max precise the current kernel > >> supports. It checks the /sys/devices/cpu/caps/max_precise. > >> > >> I think we should use that value rather than hard code it to 3. > > I'll add an extra patch to do that. I'm a bit concerned it may break > > event parsing on platforms not supporting max_precise of 3. > > The kernel already rejects the precise_ip > max_precise (using the same > x86_pmu_max_precise()). It should be fine to apply the same logic in the > tool. > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/a= rch/x86/events/core.c#n566 > > Will the extra patch be sent separately? Let's do it separately. I'm concerned about the behavior on AMD (and possibly similar architectures) where certain events support precision like cycles, as they detour to the IBS PMU, but not all events support it. The max_precise should reflect that AMD's Zen core PMU does support precision as a consequence of detouring to IBS, but maybe things in sysfs aren't set up correctly. Thanks, Ian > Thanks, > Kan