From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C4C5C4321E for ; Fri, 2 Dec 2022 17:36:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234001AbiLBRge (ORCPT ); Fri, 2 Dec 2022 12:36:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52380 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233973AbiLBRgd (ORCPT ); Fri, 2 Dec 2022 12:36:33 -0500 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 10BCCE8E3C for ; Fri, 2 Dec 2022 09:36:28 -0800 (PST) Received: by mail-wr1-x436.google.com with SMTP id y16so8887122wrm.2 for ; Fri, 02 Dec 2022 09:36:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=tMmIbi4e/X1/uiuwY8BvO8Ud6JyyRMbx0iz80rslda4=; b=LcrCJ2TMz3+4QidtoXI756Tji9ADtZqJ62iUoXhSHHFiW0rmbyQRLemmBLmyKNAsa7 iftotDTyUGc/SP2LfHQknWNFZjbVRgzUmyLRihHVtU/RwIgZP6B5e57L1Yhm/OFRzyvp CNoNSuNyKsFwifjqqi5uLPa5lvo4JwNcJrIoTVBCsOTjrR9BkkXnmnY1i7cp0PW7gJBV ZKxsTg2TBOMI+rrFVte47+8f/BLpVW/fKUMPu8FhkS1PotgqaGbhs3e0ICFoPctNz/Ql RvhL7THGsVk44W73zzV8Xu/Jb+2ADrbZXxD4BHpOLpGqvMsQhM11XaSTa45a8ZAqzhAq kXtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=tMmIbi4e/X1/uiuwY8BvO8Ud6JyyRMbx0iz80rslda4=; b=pjk7IO0i/lO2pyYZNmpDAxm0GIzUsKuLcwRi5TFZ+WMkHVdW4TCIKF0B4qjZi8VRFn ALoO9jPT7QrTLS57mNTO/b5k10EUqVdHF1gIdWWiEB9lR2JUbFyRPZbwFA15vgrHEspX RUakLGe2pDK4OtT2GlO4bvNNdY8k1gqJZo4ytBwJQ8IjMMQ//fBDf+4lYghIuTwRy/4f UWVkmk/ogpsuW+1ZSewHyQnFzrBofLF1zvvo8hnaVfTH2oYHXK42llI5Kc/YtDiywvU5 yR48GZA/ZlSzSh9sMZr3znX78fbuoVpU22ZnnmMZ2otzHW7vJA9r6WbNJYxkXOrtNQBG hOsw== X-Gm-Message-State: ANoB5pl3Z0QnEgvxNt+6lwEQBj8wj5JtUrK72cE22Ivoc1ARS4GwoYFb PsNisG6LC6kOt/aUlzl9y0ptMgg+E1auWl8af+ym1g== X-Google-Smtp-Source: AA0mqf429zt33NbLfsZBqEmtjy/QQWT2sYU+veHHys1lkbA96+XFEq+2NvVor/amc0cuAQW+zzn3msPfSy+bKCD4Pcc= X-Received: by 2002:adf:e64f:0:b0:241:e2f1:8b44 with SMTP id b15-20020adfe64f000000b00241e2f18b44mr31351795wrn.300.1670002586412; Fri, 02 Dec 2022 09:36:26 -0800 (PST) MIME-Version: 1.0 References: <20221202135149.1797974-1-colin.i.king@gmail.com> In-Reply-To: <20221202135149.1797974-1-colin.i.king@gmail.com> From: Ian Rogers Date: Fri, 2 Dec 2022 09:36:14 -0800 Message-ID: Subject: Re: [PATCH][next] perf/x86/amd: fix potential integer overflow on shift of a int To: Colin Ian King Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Thomas Gleixner , Borislav Petkov , Dave Hansen , x86@kernel.org, "H . Peter Anvin" , Kim Phillips , linux-perf-users@vger.kernel.org, kernel-janitors@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-perf-users@vger.kernel.org On Fri, Dec 2, 2022 at 5:52 AM Colin Ian King wrote: > > The left shift of int 32 bit integer constant 1 is evaluated using 32 bit > arithmetic and then passed as a 64 bit function argument. In the case where > i is 32 or more this can lead to an overflow. Avoid this by shifting > using the BIT_ULL macro instead. > > Fixes: 471af006a747 ("perf/x86/amd: Constrain Large Increment per Cycle events") > Signed-off-by: Colin Ian King Acked-by: Ian Rogers Thanks, Ian > --- > arch/x86/events/amd/core.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c > index d6f3703e4119..4386b10682ce 100644 > --- a/arch/x86/events/amd/core.c > +++ b/arch/x86/events/amd/core.c > @@ -1387,7 +1387,7 @@ static int __init amd_core_pmu_init(void) > * numbered counter following it. > */ > for (i = 0; i < x86_pmu.num_counters - 1; i += 2) > - even_ctr_mask |= 1 << i; > + even_ctr_mask |= BIT_ULL(i); > > pair_constraint = (struct event_constraint) > __EVENT_CONSTRAINT(0, even_ctr_mask, 0, > -- > 2.38.1 >